| Message ID | e1d6913bfe5ce023d7f6ea106d0359142063e694.1637061057.git.shubhrajyoti.datta@xilinx.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart' | expand |
On Tue, Nov 16, 2021 at 04:47:45PM +0530, Shubhrajyoti Datta wrote: > Add support for Uart used in Xilinx Versal SOCs as a platform > device. No. Why would we want to do that? > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> > --- > Documentation/devicetree/bindings/serial/pl011.yaml | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml > index 5ea00f8a283d..6c73923dd15e 100644 > --- a/Documentation/devicetree/bindings/serial/pl011.yaml > +++ b/Documentation/devicetree/bindings/serial/pl011.yaml > @@ -24,9 +24,13 @@ select: > > properties: > compatible: > - items: > - - const: arm,pl011 > - - const: arm,primecell > + oneOf: > + - items: > + - const: arm,pl011 > + - const: arm,primecell > + - items: > + - const: arm,pl011 > + - const: arm,xlnx-uart # xilinx uart as platform device 'arm,primecell' means the block has ID registers. Are you saying this implementation doesn't? > > reg: > maxItems: 1 > -- > 2.25.1 > >
> -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: Tuesday, November 30, 2021 3:39 AM > To: Shubhrajyoti Datta <shubhraj@xilinx.com> > Cc: linux-serial@vger.kernel.org; devicetree@vger.kernel.org; > gregkh@linuxfoundation.org; Raviteja Narayanam <rna@xlnx.xilinx.com> > Subject: Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart' > > On Tue, Nov 16, 2021 at 04:47:45PM +0530, Shubhrajyoti Datta wrote: > > Add support for Uart used in Xilinx Versal SOCs as a platform device. > > No. Why would we want to do that? Apologies did not understand that. > > > > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > > Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> > > --- > > Documentation/devicetree/bindings/serial/pl011.yaml | 10 +++++++--- > > 1 file changed, 7 insertions(+), 3 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml > > b/Documentation/devicetree/bindings/serial/pl011.yaml > > index 5ea00f8a283d..6c73923dd15e 100644 > > --- a/Documentation/devicetree/bindings/serial/pl011.yaml > > +++ b/Documentation/devicetree/bindings/serial/pl011.yaml > > @@ -24,9 +24,13 @@ select: > > > > properties: > > compatible: > > - items: > > - - const: arm,pl011 > > - - const: arm,primecell > > + oneOf: > > + - items: > > + - const: arm,pl011 > > + - const: arm,primecell > > + - items: > > + - const: arm,pl011 > > + - const: arm,xlnx-uart # xilinx uart as platform device > > 'arm,primecell' means the block has ID registers. Are you saying this > implementation doesn't? The ID registers do not have any Xilinx specific identifiers. However there are differences like 32-bit access. > > > > > reg: > > maxItems: 1 > > -- > > 2.25.1 > > > >
<snip> > > > > diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml > > > > b/Documentation/devicetree/bindings/serial/pl011.yaml > > > > index 5ea00f8a283d..6c73923dd15e 100644 > > > > --- a/Documentation/devicetree/bindings/serial/pl011.yaml > > > > +++ b/Documentation/devicetree/bindings/serial/pl011.yaml > > > > @@ -24,9 +24,13 @@ select: > > > > > > > > properties: > > > > compatible: > > > > - items: > > > > - - const: arm,pl011 > > > > - - const: arm,primecell > > > > + oneOf: > > > > + - items: > > > > + - const: arm,pl011 > > > > + - const: arm,primecell > > > > + - items: > > > > + - const: arm,pl011 > > > > + - const: arm,xlnx-uart # xilinx uart as platform device > > > > > > 'arm,primecell' means the block has ID registers. Are you saying > > > this implementation doesn't? > > > > The ID registers do not have any Xilinx specific identifiers. > > However there are differences like 32-bit access. > > Hope that the current approach is fine with you. Could you please guide how to go about it. > > Thanks > > > > > > > > > > > reg: > > > > maxItems: 1 > > > > -- > > > > 2.25.1 > > > > > > > >
On Tue, Mar 22, 2022 at 5:59 AM Shubhrajyoti Datta <shubhraj@xilinx.com> wrote: > > <snip> > > > > > diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml > > > > > b/Documentation/devicetree/bindings/serial/pl011.yaml > > > > > index 5ea00f8a283d..6c73923dd15e 100644 > > > > > --- a/Documentation/devicetree/bindings/serial/pl011.yaml > > > > > +++ b/Documentation/devicetree/bindings/serial/pl011.yaml > > > > > @@ -24,9 +24,13 @@ select: > > > > > > > > > > properties: > > > > > compatible: > > > > > - items: > > > > > - - const: arm,pl011 > > > > > - - const: arm,primecell > > > > > + oneOf: > > > > > + - items: > > > > > + - const: arm,pl011 > > > > > + - const: arm,primecell > > > > > + - items: > > > > > + - const: arm,pl011 > > > > > + - const: arm,xlnx-uart # xilinx uart as platform device > > > > > > > > 'arm,primecell' means the block has ID registers. Are you saying > > > > this implementation doesn't? > > > > > > The ID registers do not have any Xilinx specific identifiers. > > > However there are differences like 32-bit access. > > > > Hope that the current approach is fine with you. > > Could you please guide how to go about it. No, I don't know what the differences are in your h/w. You have ID registers, but changed the IP and didn't change the ID registers? How has the IP changed? Rob
On 14/07/2022 12:55, Michal Simek wrote: > Hi Rob and Krzysztof, > > On 6/14/22 14:21, Shubhrajyoti Datta wrote: >>>> >> <snip> >> >>> >>> No, I don't know what the differences are in your h/w. You have ID >>> registers, but changed the IP and didn't change the ID registers? How >>> has the IP changed? >>> >> >> The IP is not changed and the ID registers are not updated. >> The limitation is coming from the AXI port that the IP is connected to. >> The axi port is allowing only the 32 bit access. >> The same information will be updated in the Versal TRM. > > Can you please give us your recommendation how to process with this? Unfortunately I don't think that anyone remembers context from last year, especially me who was not Cced. Rob responded at end of March and it took two months to get back any answer. Such slow response time from submitter does not help to stay in the context. :( Best regards, Krzysztof
On 7/14/22 14:14, Datta, Shubhrajyoti wrote: > [AMD Official Use Only - General] > > > >> -----Original Message----- >> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> Sent: Thursday, July 14, 2022 5:29 PM >> To: Michal Simek <michal.simek@xilinx.com>; Shubhrajyoti Datta >> <shubhrajyoti.datta@gmail.com>; Rob Herring <robh@kernel.org>; Krzysztof >> Kozlowski <krzysztof.kozlowski+dt@linaro.org> >> Cc: Shubhrajyoti Datta <shubhraj@xilinx.com>; linux-serial@vger.kernel.org; >> devicetree@vger.kernel.org; gregkh@linuxfoundation.org; Srinivas Goud >> <sgoud@xilinx.com> >> Subject: Re: [PATCH 1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart' >> >> CAUTION: This message has originated from an External Source. Please use >> proper judgment and caution when opening attachments, clicking links, or >> responding to this email. >> >> >> On 14/07/2022 12:55, Michal Simek wrote: >>> Hi Rob and Krzysztof, >>> >>> On 6/14/22 14:21, Shubhrajyoti Datta wrote: >>>>>> >>>> <snip> >>>> >>>>> >>>>> No, I don't know what the differences are in your h/w. You have ID >>>>> registers, but changed the IP and didn't change the ID registers? >>>>> How has the IP changed? >>>>> >>>> >>>> The IP is not changed and the ID registers are not updated. >>>> The limitation is coming from the AXI port that the IP is connected to. >>>> The axi port is allowing only the 32 bit access. >>>> The same information will be updated in the Versal TRM. >>> >>> Can you please give us your recommendation how to process with this? >> >> Unfortunately I don't think that anyone remembers context from last year, >> especially me who was not Cced. Rob responded at end of March and it took >> two months to get back any answer. Such slow response time from submitter >> does not help to stay in the context. :( > > I had to contact the hardware team and get the details on the issue it took me sometime to get a response. > > I will summarize > > We are using the ip from ARM but the AXI port that we hooked has a limitation that it allows only 32 bit accesses. > > So to tide over the and differentiate I am adding a new compatible arm,xlnx-uart. ok. Shubhrajyoti: Please send this series again with updated commit message in 1/2 which contains information you provided here. That means it will be v2 version. Thanks, Michal
diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml index 5ea00f8a283d..6c73923dd15e 100644 --- a/Documentation/devicetree/bindings/serial/pl011.yaml +++ b/Documentation/devicetree/bindings/serial/pl011.yaml @@ -24,9 +24,13 @@ select: properties: compatible: - items: - - const: arm,pl011 - - const: arm,primecell + oneOf: + - items: + - const: arm,pl011 + - const: arm,primecell + - items: + - const: arm,pl011 + - const: arm,xlnx-uart # xilinx uart as platform device reg: maxItems: 1