Message ID | 20211216202614.414266-46-clg@kaod.org |
---|---|
State | Accepted |
Commit | 8ea0b1408e680ecd08a48c51fb1e4d0ec8cbdc15 |
Headers | show
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Thu, 16 Dec 2021 20:26:49 +0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1BGKQlNd29950328 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 Dec 2021 20:26:47 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 172FB52051; Thu, 16 Dec 2021 20:26:47 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with SMTP id D2A555204E; Thu, 16 Dec 2021 20:26:46 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.48.122]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 3D511220238; Thu, 16 Dec 2021 21:26:46 +0100 (CET) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org> To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 045/101] target/ppc: Update fre to new flags Date: Thu, 16 Dec 2021 21:25:18 +0100 Message-Id: <20211216202614.414266-46-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211216202614.414266-1-clg@kaod.org> References: <20211216202614.414266-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; 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diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 853e0aad1d4e..aef81a818f63 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -765,20 +765,15 @@ float64 helper_fre(CPUPPCState *env, float64 arg) { /* "Estimate" the reciprocal with actual division. */ float64 ret = float64_div(float64_one, arg, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status)) { - if (status & float_flag_invalid) { - if (float64_is_signaling_nan(arg, &env->fp_status)) { - /* sNaN reciprocal */ - float_invalid_op_vxsnan(env, GETPC()); - } - } - if (status & float_flag_divbyzero) { - float_zero_divide_excp(env, GETPC()); - /* For FPSCR.ZE == 0, the result is 1/2. */ - ret = float64_set_sign(float64_half, float64_is_neg(arg)); - } + if (unlikely(flags & float_flag_invalid_snan)) { + float_invalid_op_vxsnan(env, GETPC()); + } + if (unlikely(flags & float_flag_divbyzero)) { + float_zero_divide_excp(env, GETPC()); + /* For FPSCR.ZE == 0, the result is 1/2. */ + ret = float64_set_sign(float64_half, float64_is_neg(arg)); } return ret;