| Message ID | 1440942866-23802-10-git-send-email-christoffer.dall@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 30 August 2015 at 15:54, Christoffer Dall <christoffer.dall@linaro.org> wrote: > Provide a better quality of implementation and be architecture compliant > on ARMv7 for the architected timer by resetting the CNTV_CTL to 0 on > reset of the timer, and call kvm_timer_update_state(vcpu) at the same > time, ensuring the timer output is not asserted after, for example, a > PSCI system reset. > > This change alone fixes the UEFI reset issue reported by Laszlo back in > February. > Do you have a link to that report? I can't quite remember the details ... > Cc: Laszlo Ersek <lersek@redhat.com> > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> > Cc: Drew Jones <drjones@redhat.com> > Cc: Wei Huang <wei@redhat.com> > Cc: Peter Maydell <peter.maydell@linaro.org> > Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> > --- > virt/kvm/arm/arch_timer.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c > index 747302f..8a0fdfc 100644 > --- a/virt/kvm/arm/arch_timer.c > +++ b/virt/kvm/arm/arch_timer.c > @@ -255,6 +255,15 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu, > timer->irq.irq = irq->irq; > > /* > + * The bits in CNTV_CTL are architecturally reset to UNKNOWN for ARMv8 > + * and to 0 for ARMv7. We provide an implementation that always > + * resets the timer to be disabled and unmasked and is compliant with > + * the ARMv7 architecture. > + */ > + timer->cntv_ctl = 0; > + kvm_timer_update_state(vcpu); > + > + /* > * Tell the VGIC that the virtual interrupt is tied to a > * physical interrupt. We do that once per VCPU. > */ > -- > 2.1.2.330.g565301e.dirty >
On Mon, Aug 31, 2015 at 10:46:59AM +0200, Ard Biesheuvel wrote: > On 30 August 2015 at 15:54, Christoffer Dall > <christoffer.dall@linaro.org> wrote: > > Provide a better quality of implementation and be architecture compliant > > on ARMv7 for the architected timer by resetting the CNTV_CTL to 0 on > > reset of the timer, and call kvm_timer_update_state(vcpu) at the same > > time, ensuring the timer output is not asserted after, for example, a > > PSCI system reset. > > > > This change alone fixes the UEFI reset issue reported by Laszlo back in > > February. > > > > Do you have a link to that report? I can't quite remember the details ... > There was no public mailing list cc'ed on the report, and the bugzilla bug was created in a non-public Red Hat instance. But you were cc'ed on the original mail from Laszlo. Look for an e-mail from February 5th with the subject "virtual timer interrupt stuck across guest firmware reboot on KVM". -Christoffer
On 31 August 2015 at 10:57, Christoffer Dall <christoffer.dall@linaro.org> wrote: > On Mon, Aug 31, 2015 at 10:46:59AM +0200, Ard Biesheuvel wrote: >> On 30 August 2015 at 15:54, Christoffer Dall >> <christoffer.dall@linaro.org> wrote: >> > Provide a better quality of implementation and be architecture compliant >> > on ARMv7 for the architected timer by resetting the CNTV_CTL to 0 on >> > reset of the timer, and call kvm_timer_update_state(vcpu) at the same >> > time, ensuring the timer output is not asserted after, for example, a >> > PSCI system reset. >> > >> > This change alone fixes the UEFI reset issue reported by Laszlo back in >> > February. >> > >> >> Do you have a link to that report? I can't quite remember the details ... >> > There was no public mailing list cc'ed on the report, and the bugzilla > bug was created in a non-public Red Hat instance. > > But you were cc'ed on the original mail from Laszlo. Look for an e-mail > from February 5th with the subject "virtual timer interrupt stuck across > guest firmware reboot on KVM". > Found it, thanks.
On 30/08/15 14:54, Christoffer Dall wrote: > Provide a better quality of implementation and be architecture compliant > on ARMv7 for the architected timer by resetting the CNTV_CTL to 0 on > reset of the timer, and call kvm_timer_update_state(vcpu) at the same > time, ensuring the timer output is not asserted after, for example, a > PSCI system reset. > > This change alone fixes the UEFI reset issue reported by Laszlo back in > February. > > Cc: Laszlo Ersek <lersek@redhat.com> > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> > Cc: Drew Jones <drjones@redhat.com> > Cc: Wei Huang <wei@redhat.com> > Cc: Peter Maydell <peter.maydell@linaro.org> > Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> M.
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index 747302f..8a0fdfc 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -255,6 +255,15 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu, timer->irq.irq = irq->irq; /* + * The bits in CNTV_CTL are architecturally reset to UNKNOWN for ARMv8 + * and to 0 for ARMv7. We provide an implementation that always + * resets the timer to be disabled and unmasked and is compliant with + * the ARMv7 architecture. + */ + timer->cntv_ctl = 0; + kvm_timer_update_state(vcpu); + + /* * Tell the VGIC that the virtual interrupt is tied to a * physical interrupt. We do that once per VCPU. */
Provide a better quality of implementation and be architecture compliant on ARMv7 for the architected timer by resetting the CNTV_CTL to 0 on reset of the timer, and call kvm_timer_update_state(vcpu) at the same time, ensuring the timer output is not asserted after, for example, a PSCI system reset. This change alone fixes the UEFI reset issue reported by Laszlo back in February. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Drew Jones <drjones@redhat.com> Cc: Wei Huang <wei@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> --- virt/kvm/arm/arch_timer.c | 9 +++++++++ 1 file changed, 9 insertions(+)