[RFC,V1,3/8] clk: Add support for simple dividers

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 8f8e7ac..979d4df 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -20,6 +20,10 @@  config GENERIC_CLK_BASIC
 	   Allow use of basic, single-function clock types.  These
 	   common definitions can be used across many platforms.
 
+config GENERIC_CLK_DIVIDER
+	bool
+	depends on GENERIC_CLK
+
 config GENERIC_CLK_SYSFS
 	bool "Clock tree topology and debug info"
 	depends on EXPERIMENTAL && GENERIC_CLK
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 806a9999..894ff3f 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -2,4 +2,5 @@ 
 obj-$(CONFIG_CLKDEV_LOOKUP)		+= clkdev.o
 obj-$(CONFIG_GENERIC_CLK)		+= clk.o
 obj-$(CONFIG_GENERIC_CLK_BASIC)		+= clk-basic.o
+obj-$(CONFIG_GENERIC_CLK_DIVIDER)	+= clk-divider.o
 obj-$(CONFIG_GENERIC_CLK_SYSFS)		+= clk-sysfs.o
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
new file mode 100644
index 0000000..7af9f6f
--- /dev/null
+++ b/drivers/clk/clk-divider.c
@@ -0,0 +1,132 @@ 
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Standard functionality for the common clock API.
+ */
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#define to_clk_divider(ck) container_of(ck, struct clk_divider, clk)
+
+static unsigned long clk_divider_recalc_rate(struct clk *clk)
+{
+	struct clk_divider *divider = to_clk_divider(clk);
+	unsigned long rate = clk->parent->rate;
+	unsigned int div;
+
+	div = readl(divider->reg) >> divider->shift;
+	div &= (1 << divider->width) - 1;
+
+	if (!(divider->flags & CLK_DIVIDER_FLAG_ONE_BASED))
+		div++;
+
+	return rate / div;
+}
+
+#define account_for_rounding_errors	1
+
+static int clk_divider_bestdiv(struct clk *clk, unsigned long rate,
+		unsigned long *best_parent_rate)
+{
+	struct clk_divider *divider = to_clk_divider(clk);
+	int i, bestdiv = 0;
+	unsigned long parent_rate, best = 0, now, maxdiv;
+
+	maxdiv = (1 << divider->width);
+
+	if (divider->flags & CLK_DIVIDER_FLAG_ONE_BASED)
+		maxdiv--;
+
+	if (!(clk->flags & CLK_PARENT_SET_RATE)) {
+		parent_rate = clk->parent->rate;
+		bestdiv = parent_rate / rate;
+		bestdiv = bestdiv == 0 ? 1 : bestdiv;
+		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
+		goto out;
+	}
+
+	/*
+	 * The maximum divider we can use without overflowing
+	 * unsigned long in rate * i below
+	 */
+	maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+	for (i = 1; i <= maxdiv; i++) {
+		parent_rate = clk_round_rate(clk->parent,
+				(rate + account_for_rounding_errors) * i);
+		now = parent_rate / i;
+
+		if (now <= rate && now >= best) {
+			bestdiv = i;
+			best = now;
+		}
+	}
+
+	if (!bestdiv) {
+		bestdiv = (1 << divider->width);
+		parent_rate = clk_round_rate(clk->parent, 1);
+	} else {
+		parent_rate = best * bestdiv;
+	}
+
+out:
+	if (best_parent_rate)
+		*best_parent_rate = parent_rate;
+
+	return bestdiv;
+}
+
+static long clk_divider_round_rate(struct clk *clk, unsigned long rate,
+				unsigned long *prate)
+{
+	unsigned long best_parent_rate;
+	int div = clk_divider_bestdiv(clk, rate, &best_parent_rate);
+	if (prate) {
+		if (best_parent_rate == clk->parent->rate)
+			*prate = 0;
+		else
+			*prate = best_parent_rate;
+	}
+
+	return best_parent_rate / div;
+}
+
+static int clk_divider_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long best_parent_rate;
+	struct clk_divider *divider = to_clk_divider(clk);
+	unsigned int div;
+	unsigned long flags = 0;
+	u32 val;
+
+	div = clk_divider_bestdiv(clk, rate, &best_parent_rate);
+
+	if (divider->lock)
+		spin_lock_irqsave(divider->lock, flags);
+
+	if (!(divider->flags & CLK_DIVIDER_FLAG_ONE_BASED))
+		div--;
+
+	val = readl(divider->reg);
+	val &= ~(((1 << divider->width) - 1) << divider->shift);
+	val |= div << divider->shift;
+	writel(val, divider->reg);
+
+	if (divider->lock)
+		spin_unlock_irqrestore(divider->lock, flags);
+
+	return 0;
+}
+
+struct clk_hw_ops clk_divider_ops = {
+	.recalc_rate = clk_divider_recalc_rate,
+	.round_rate = clk_divider_round_rate,
+	.set_rate = clk_divider_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_divider_ops);
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 99337ca..1a6c81c 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -168,6 +168,40 @@  int clk_register_gate(struct device *dev, const char *name, unsigned long flags,
 
 #endif
 
+#ifdef CONFIG_GENERIC_CLK_DIVIDER
+
+#include <linux/spinlock.h>
+
+/**
+ * clock divider
+ *
+ * @clk		clock source
+ * @reg		register containing the divider
+ * @shift	shift to the divider
+ * @width	width of the divider
+ * @lock	register lock
+ *
+ * This clock implements get_rate/set_rate/round_rate.
+ *
+ * The divider is calculated as div = reg_val + 1
+ * or if CLK_DIVIDER_FLAG_ONE_BASED is set as div = reg_val
+ * (with reg_val == 0 considered invalid)
+ */
+struct clk_divider {
+	struct clk	clk;
+	void __iomem	*reg;
+	unsigned char	shift;
+	unsigned char	width;
+	spinlock_t	*lock;
+#define CLK_DIVIDER_FLAG_ONE_BASED		(1 << 0)
+	unsigned int	flags;
+	struct clk_hw	*parent;
+};
+
+extern struct clk_hw_ops clk_divider_ops;
+
+#endif /* CONFIG_GENERIC_CLK_DIVIDER */
+
 /**
  * clk_init - initialize the data structures in a struct clk
  * @dev: device initializing this clk, placeholder for now