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[RFC,V1,4/8] clk: Add support for a generic clock multiplexer

Message ID 1322046755-13511-5-git-send-email-richard.zhao@linaro.org
State RFC
Headers show

Commit Message

Richard Zhao Nov. 23, 2011, 11:12 a.m. UTC 
This patch adds support for a common type of clock multiplexer.
The multiplexer is described with register, shift and width and
an array of clocks which correspond to the bit value.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
---
 drivers/clk/Kconfig   |    4 +++
 drivers/clk/Makefile  |    1 +
 drivers/clk/clk-mux.c |   64 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk.h   |   33 +++++++++++++++++++++++++
 4 files changed, 102 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-mux.c
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Patch

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 979d4df..fadbcdd 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -24,6 +24,10 @@  config GENERIC_CLK_DIVIDER
 	bool
 	depends on GENERIC_CLK
 
+config GENERIC_CLK_MUX
+	bool
+	depends on GENERIC_CLK
+
 config GENERIC_CLK_SYSFS
 	bool "Clock tree topology and debug info"
 	depends on EXPERIMENTAL && GENERIC_CLK
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 894ff3f..4327715 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -3,4 +3,5 @@  obj-$(CONFIG_CLKDEV_LOOKUP)		+= clkdev.o
 obj-$(CONFIG_GENERIC_CLK)		+= clk.o
 obj-$(CONFIG_GENERIC_CLK_BASIC)		+= clk-basic.o
 obj-$(CONFIG_GENERIC_CLK_DIVIDER)	+= clk-divider.o
+obj-$(CONFIG_GENERIC_CLK_MUX)		+= clk-mux.o
 obj-$(CONFIG_GENERIC_CLK_SYSFS)		+= clk-sysfs.o
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
new file mode 100644
index 0000000..05e813e
--- /dev/null
+++ b/drivers/clk/clk-mux.c
@@ -0,0 +1,64 @@ 
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Standard functionality for the common clock API.
+ */
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#define to_clk_mux(ck) container_of(ck, struct clk_mux, clk)
+
+static struct clk *clk_mux_get_parent(struct clk *clk)
+{
+	struct clk_mux *mux = to_clk_mux(clk);
+	u32 val;
+
+	val = readl(mux->reg) >> mux->shift;
+	val &= (1 << mux->width) - 1;
+
+	if (val >= mux->num_clks)
+		return ERR_PTR(-EINVAL);
+
+	return mux->clks[val];
+}
+
+static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct clk_mux *mux = to_clk_mux(clk);
+	u32 val;
+	int i;
+	unsigned long flags = 0;
+
+	for (i = 0; i < mux->num_clks; i++)
+		if (mux->clks[i] == parent)
+			break;
+
+	if (i == mux->num_clks)
+		return -EINVAL;
+
+	if (mux->lock)
+		spin_lock_irqsave(mux->lock, flags);
+
+	val = readl(mux->reg);
+	val &= ~(((1 << mux->width) - 1) << mux->shift);
+	val |= i << mux->shift;
+	writel(val, mux->reg);
+
+	if (mux->lock)
+		spin_unlock_irqrestore(mux->lock, flags);
+
+	return 0;
+}
+
+struct clk_hw_ops clk_mux_ops = {
+	.get_parent = clk_mux_get_parent,
+	.set_parent = clk_mux_set_parent,
+};
+EXPORT_SYMBOL_GPL(clk_mux_ops);
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 1a6c81c..2b65a69 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -202,6 +202,39 @@  extern struct clk_hw_ops clk_divider_ops;
 
 #endif /* CONFIG_GENERIC_CLK_DIVIDER */
 
+#ifdef CONFIG_GENERIC_CLK_MUX
+
+#include <linux/spinlock.h>
+
+/**
+ * clock multiplexer
+ *
+ * @reg		the register this multiplexer can be configured with
+ * @shift	the shift to the start bit of this multiplexer
+ * @width	the width in bits of this multiplexer
+ * @num_clks	number of parent clocks
+ * @lock	register lock
+ * @clks	array of possible parents for this multiplexer. Can contain
+ *		holes with NULL in it for invalid register settings
+ *
+ * This clock implements get_parent/set_parent. prepare/unprepare,
+ * enable/disable and get_rate operations are passed through to the parent,
+ * the rate is not adjustable.
+ */
+struct clk_mux {
+	struct clk	clk;
+	void __iomem	*reg;
+	unsigned char	shift;
+	unsigned char	width;
+	unsigned char	num_clks;
+	spinlock_t	*lock;
+	struct clk	**clks;
+};
+
+extern struct clk_hw_ops clk_mux_ops;
+
+#endif /* CONFIG_GENERIC_CLK_MUX */
+
 /**
  * clk_init - initialize the data structures in a struct clk
  * @dev: device initializing this clk, placeholder for now