diff mbox

[RFC,V1,7/8] ARM i.MX: prepare common clk support

Message ID 1322046755-13511-8-git-send-email-richard.zhao@linaro.org
State RFC
Headers show

Commit Message

Richard Zhao Nov. 23, 2011, 11:12 a.m. UTC 
From: Sascha Hauer <s.hauer@pengutronix.de>

Add static clock help macros, clock register spinlock.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
---
 arch/arm/plat-mxc/clock.c              |    8 ++++
 arch/arm/plat-mxc/include/mach/clock.h |   63 ++++++++++++++++++++++++++++++--
 2 files changed, 68 insertions(+), 3 deletions(-)
diff mbox

Patch

diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 2ed3ab1..1973b30 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -41,6 +41,8 @@ 
 #include <mach/clock.h>
 #include <mach/hardware.h>
 
+#ifndef CONFIG_GENERIC_CLK
+
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
 
@@ -199,6 +201,7 @@  struct clk *clk_get_parent(struct clk *clk)
 	return clk->parent;
 }
 EXPORT_SYMBOL(clk_get_parent);
+#endif
 
 /*
  * Get the resulting clock rate from a PLL register value and the input
@@ -244,3 +247,8 @@  unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
 
 	return ll;
 }
+
+#ifdef CONFIG_GENERIC_CLK
+DEFINE_SPINLOCK(imx_ccm_lock);
+EXPORT_SYMBOL_GPL(imx_ccm_lock);
+#endif /* CONFIG_USE_COMMON_STRUCT_CLK */
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index f62256e..b9cfb46 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -81,9 +81,13 @@  struct clk_pllv2 {
 
 extern struct clk_hw_ops clk_pllv2_ops;
 
-#define DEFINE_CLK_PLLV2(name, _parent, _base) \
-	struct clk_pllv2 name = { \
-		.parent = (_parent), \
+#define DEFINE_CLK_PLLV2(_name, _parent, _base) \
+	struct clk_pllv2 _name = { \
+		.clk = { \
+			.name = #_name, \
+			.ops = &clk_pllv2_ops, \
+			.parent = _parent, \
+		}, \
 		.base = (_base), \
 	}
 
@@ -109,6 +113,59 @@  extern struct clk_hw_ops clk_gate2b_ops;
 
 int clk_gate2b_set_val(struct clk *clk, int en, int dis);
 
+extern spinlock_t imx_ccm_lock;
+
+#define DEFINE_CLK_GATE2B(_name, _parent, _reg, _shift) \
+	struct clk_gate2b _name = { \
+		.clk = { \
+			.name = #_name, \
+			.ops = &clk_gate2b_ops, \
+			.parent = _parent, \
+		}, \
+		.reg = (_reg), \
+		.shift = (_shift) * 2, \
+		.val_en = 0x3, \
+		.val_dis = 0x0, \
+		.lock = &imx_ccm_lock, \
+	}
+
+#define DEFINE_CLK_DIVIDER(_name, _parent, _flags, _reg, _shift, _width) \
+	struct clk_divider _name = { \
+		.clk = { \
+			.name = #_name, \
+			.ops = &clk_divider_ops, \
+			.parent = _parent, \
+			.flags = _flags, \
+		}, \
+		.reg = (_reg), \
+		.shift = (_shift), \
+		.width = (_width), \
+		.lock = &imx_ccm_lock, \
+	}
+
+#define DEFINE_CLK_MUX(_name, _reg, _shift, _width, _clks) \
+	struct clk_mux _name = { \
+		.clk = { \
+			.name = #_name, \
+			.ops = &clk_mux_ops, \
+		}, \
+		.reg = (_reg), \
+		.shift = (_shift), \
+		.width = (_width), \
+		.clks = (_clks), \
+		.num_clks = ARRAY_SIZE(_clks), \
+		.lock = &imx_ccm_lock, \
+	}
+
+#define DEFINE_CLK_FIXED(_name, _rate) \
+	struct clk_hw_fixed _name = { \
+		.clk = { \
+			.name = #_name, \
+			.ops = &clk_hw_fixed_ops, \
+		}, \
+		.fixed_rate = (_rate), \
+	}
+
 #endif /* CONFIG_GENERIC_CLK */
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_ARCH_MXC_CLOCK_H__ */