| Message ID | 20220128062902.26273-3-chunfeng.yun@mediatek.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/4] dt-bindings: usb: mtk-xhci: add support ip-sleep for mt8195 | expand |
Il 28/01/22 07:29, Chunfeng Yun ha scritto: > Add efuse node and cells used by t-phy to fix the bit shift issue > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On 2/11/22 6:17 PM, Greg Kroah-Hartman wrote: > On Fri, Jan 28, 2022 at 02:29:01PM +0800, Chunfeng Yun wrote: >> Add efuse node and cells used by t-phy to fix the bit shift issue >> >> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> >> --- >> v2: use hw auto load for u2phy which has no this issue >> >> Note: >> >> depend on the reviewing patch: >> >> [v9,3/3] arm64: dts: Add mediatek SoC mt8195 and evaluation board >> https://urldefense.com/v3/__https://patchwork.kernel.org/patch/12711296__;!!CTRNKA9wMg0ARbw!0Jg8kLN4kBw0LcbiAH1HYTq2uQ5VwiD-CE8yoFBD7oApn8YNSdmVpwSdY1q2C7LvY6c$ > > As I don't have that in my tree, I can only take the first 2 patches > here now, thanks. > > greg k-h > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!0Jg8kLN4kBw0LcbiAH1HYTq2uQ5VwiD-CE8yoFBD7oApn8YNSdmVpwSdY1q2ZMDXmG4$ > Just a gentle reminder that there is new v10 version [1] [PATCH v10 3/3] arm64: dts: Add mediatek SoC mt8195 and evaluation board https://lore.kernel.org/lkml/20220130023209.16275-4-tinghan.shen@mediatek.com/T/#mae7fce60ae5402e7a5d044fb27ce07d9f0db03ce Come along with this patch set is still under reviewing. [2] [PATCH v10 0/3] Add basic SoC support for mediatek mt8195 https://lore.kernel.org/lkml/20220130023209.16275-4-tinghan.shen@mediatek.com/T/ While the v10 [PATCH 2/3] included in v10 patchset [2] is required for this review feedback. [3] https://lkml.org/lkml/2022/1/29/401 Thanks! Macpaul Lin
On Wed, 2022-02-16 at 17:38 +0800, Macpaul Lin wrote: > > On 2/11/22 6:17 PM, Greg Kroah-Hartman wrote: > > On Fri, Jan 28, 2022 at 02:29:01PM +0800, Chunfeng Yun wrote: > > > Add efuse node and cells used by t-phy to fix the bit shift issue > > > > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > > > --- > > > v2: use hw auto load for u2phy which has no this issue > > > > > > Note: > > > > > > depend on the reviewing patch: > > > > > > [v9,3/3] arm64: dts: Add mediatek SoC mt8195 and evaluation board > > > https://urldefense.com/v3/__https://patchwork.kernel.org/patch/12711296__;!!CTRNKA9wMg0ARbw!0Jg8kLN4kBw0LcbiAH1HYTq2uQ5VwiD-CE8yoFBD7oApn8YNSdmVpwSdY1q2C7LvY6c$ > > > > As I don't have that in my tree, I can only take the first 2 > > patches > > here now, thanks. > > > > greg k-h > > > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > Tested-by: Macpaul Lin <macpaul.lin@mediatek.com> This patch has been tested with: - "for-next" branch in MediaTek tree [1]. https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git - added more debug log to confirm efuse probing status at my local. - If probe success, it won't show any log. Thanks Macpaul Lin
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index a363e82f6988..240a21708806 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -695,6 +695,53 @@ status = "disabled"; }; + efuse: efuse@11c10000 { + compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; + reg = <0 0x11c10000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + u3_tx_imp_p0: usb3-tx-imp@184 { + reg = <0x184 0x1>; + bits = <0 5>; + }; + u3_rx_imp_p0: usb3-rx-imp@184 { + reg = <0x184 0x2>; + bits = <5 5>; + }; + u3_intr_p0: usb3-intr@185 { + reg = <0x185 0x1>; + bits = <2 6>; + }; + comb_tx_imp_p1: usb3-tx-imp@186 { + reg = <0x186 0x1>; + bits = <0 5>; + }; + comb_rx_imp_p1: usb3-rx-imp@186 { + reg = <0x186 0x2>; + bits = <5 5>; + }; + comb_intr_p1: usb3-intr@187 { + reg = <0x187 0x1>; + bits = <2 6>; + }; + u2_intr_p0: usb2-intr-p0@188 { + reg = <0x188 0x1>; + bits = <0 5>; + }; + u2_intr_p1: usb2-intr-p1@188 { + reg = <0x188 0x2>; + bits = <5 5>; + }; + u2_intr_p2: usb2-intr-p2@189 { + reg = <0x189 0x1>; + bits = <2 5>; + }; + u2_intr_p3: usb2-intr-p3@189 { + reg = <0x189 0x2>; + bits = <7 5>; + }; + }; + u3phy2: t-phy@11c40000 { compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; #address-cells = <1>; @@ -877,6 +924,10 @@ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; clock-names = "ref", "da_ref"; + nvmem-cells = <&comb_intr_p1>, + <&comb_rx_imp_p1>, + <&comb_tx_imp_p1>; + nvmem-cell-names = "intr", "rx_imp", "tx_imp"; #phy-cells = <1>; }; }; @@ -901,6 +952,10 @@ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, <&topckgen CLK_TOP_SSUSB_PHY_REF>; clock-names = "ref", "da_ref"; + nvmem-cells = <&u3_intr_p0>, + <&u3_rx_imp_p0>, + <&u3_tx_imp_p0>; + nvmem-cell-names = "intr", "rx_imp", "tx_imp"; #phy-cells = <1>; }; };
Add efuse node and cells used by t-phy to fix the bit shift issue Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> --- v2: use hw auto load for u2phy which has no this issue Note: depend on the reviewing patch: [v9,3/3] arm64: dts: Add mediatek SoC mt8195 and evaluation board https://patchwork.kernel.org/patch/12711296 --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 55 ++++++++++++++++++++++++ 1 file changed, 55 insertions(+)