@@ -208,7 +208,10 @@
pinctrl-0 = <&nandflash_pins>;
ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts = <100>;
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
@@ -519,7 +519,10 @@
pinctrl-0 = <&nandflash_pins_s0>;
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts = <100>;
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
@@ -129,7 +129,10 @@
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&intc>;
+ interrupts = <100>;
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
gpmc,device-width = <1>;
@@ -823,6 +823,10 @@
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
status = "disabled";
};
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC driver now implements gpiochip and irqchip so enable gpio-controller and interrupt-controller properties. With this the interrupt parent of NAND node changes so fix it accordingly. Signed-off-by: Roger Quadros <rogerq@ti.com> --- arch/arm/boot/dts/am335x-chilisom.dtsi | 3 +++ arch/arm/boot/dts/am335x-evm.dts | 3 +++ arch/arm/boot/dts/am335x-igep0033.dtsi | 3 +++ arch/arm/boot/dts/am33xx.dtsi | 4 ++++ 4 files changed, 13 insertions(+)