@@ -800,6 +800,7 @@
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
@@ -818,11 +819,9 @@
gpmc,access-ns = <30>;
gpmc,rd-cycle-ns = <40>;
gpmc,wr-cycle-ns = <40>;
- gpmc,wait-pin = <0>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
@@ -567,6 +567,7 @@
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
@@ -585,11 +586,9 @@
gpmc,access-ns = <30>; /* tCEA + 4*/
gpmc,rd-cycle-ns = <40>;
gpmc,wr-cycle-ns = <40>;
- gpmc,wait-pin = <0>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
On these boards NAND ready pin status is avilable over GPMC_WAIT0 pin. For NAND we don't use GPMC wait pin monitoring but get the NAND Ready/Busy# status using GPIOlib. GPMC driver provides the WAIT0 pin status over GPIOlib. Read speed increases from 16516 KiB/ to 18813 KiB/s and write speed was unchanged at 9941 KiB/s. Measured using mtd_speedtest.ko. Signed-off-by: Roger Quadros <rogerq@ti.com> --- arch/arm/boot/dts/am437x-gp-evm.dts | 3 +-- arch/arm/boot/dts/am43x-epos-evm.dts | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-)