[v1] arm64: dts: qcom: sc7280: Fix pcie gpio entries

Current gpio's in IDP file are not mapping properly,
seeing device timedout failures.

Corrected pcie gpio entries in dtsi files.

Fixes: 4e24d227aa77 ("arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board")

Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 35 ++++++++++++++------------------
 arch/arm64/boot/dts/qcom/sc7280.dtsi     | 10 ++++++++-
 2 files changed, 24 insertions(+), 21 deletions(-)

Quoting Prasad Malisetty (2022-02-02 00:21:22)
> Current gpio's in IDP file are not mapping properly,
> seeing device timedout failures.

What's the problem exactly?

>
> Corrected pcie gpio entries in dtsi files.
>
> Fixes: 4e24d227aa77 ("arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board")
>
> Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 35 ++++++++++++++------------------
>  arch/arm64/boot/dts/qcom/sc7280.dtsi     | 10 ++++++++-
>  2 files changed, 24 insertions(+), 21 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> index 78da9ac..84bf9d2 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> @@ -243,9 +243,6 @@
>         perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
>
>         vddpe-3v3-supply = <&nvme_3v3_regulator>;
> -
> -       pinctrl-names = "default";
> -       pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>;
>  };
>
>  &pcie1_phy {
> @@ -360,6 +357,21 @@
>
>  /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>
> +&pcie1_reset_n {
> +       pins = "gpio2";
> +
> +       drive-strength = <16>;

Is drive-strength of 16 actually necessary?

> +       output-low;
> +       bias-disable;
> +};
> +
> +&pcie1_wake_n {
> +       pins = "gpio3";
> +
> +       drive-strength = <2>;
> +       bias-pull-up;
> +};
> +
>  &pm7325_gpios {
>         key_vol_up_default: key-vol-up-default {
>                 pins = "gpio6";
> @@ -436,23 +448,6 @@
>                 function = "gpio";
>         };
>
> -       pcie1_reset_n: pcie1-reset-n {
> -               pins = "gpio2";
> -               function = "gpio";
> -
> -               drive-strength = <16>;
> -               output-low;
> -               bias-disable;
> -       };
> -
> -       pcie1_wake_n: pcie1-wake-n {
> -               pins = "gpio3";
> -               function = "gpio";
> -
> -               drive-strength = <2>;
> -               bias-pull-up;
> -       };
> -
>         qup_uart7_sleep_cts: qup-uart7-sleep-cts {
>                 pins = "gpio28";
>                 function = "gpio";
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index d4009cc..2e14c37 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1640,7 +1640,7 @@
>                         phy-names = "pciephy";
>
>                         pinctrl-names = "default";
> -                       pinctrl-0 = <&pcie1_clkreq_n>;
> +                       pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>;
>
>                         iommus = <&apps_smmu 0x1c80 0x1>;
>
> @@ -3272,6 +3272,14 @@
>                                 bias-pull-up;
>                         };
>
> +                       pcie1_reset_n: pcie1-reset-n {
> +                               function = "gpio";
> +                       };
> +
> +                       pcie1_wake_n: pcie1-wake-n {
> +                               function = "gpio";
> +                       };
> +
>                         dp_hot_plug_det: dp-hot-plug-det {
>                                 pins = "gpio47";
>                                 function = "dp_hot";
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>