| Message ID | 1644591438-6514-3-git-send-email-quic_srivasam@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add soundcard support for sc7280 based platforms. | expand |
Hi, On Fri, Feb 11, 2022 at 6:57 AM Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> wrote: > > @@ -1750,6 +1751,64 @@ > #clock-cells = <1>; > }; > > + lpass_cpu: audio-subsystem@3260000 { > + compatible = "qcom,sc7280-lpass-cpu"; > + reg = <0 0x3260000 0 0xC000>, > + <0 0x3280000 0 0x29000>, > + <0 0x3340000 0 0x29000>, > + <0 0x336C000 0 0x3000>, > + <0 0x3987000 0 0x68000>, > + <0 0x3B00000 0 0x29000>; Lower case hex, please. ...and pad the address to 8 digits here (just don't do it in the unit address in the node name). > + reg-names = "lpass-rxtx-cdc-dma-lpm", > + "lpass-rxtx-lpaif", > + "lpass-va-lpaif", > + "lpass-va-cdc-dma-lpm", > + "lpass-hdmiif", > + "lpass-lpaif"; The order of "reg" and "reg-names" needs to match the bindings exactly. It's almost certainly easier to change your device tree since the bindings have already landed. That means that "lpass-hdmiif" will be first. ...and it will also change your node name since the first "reg" listed will now be 3987000. > + iommus = <&apps_smmu 0x1820 0>, > + <&apps_smmu 0x1821 0>, > + <&apps_smmu 0x1832 0>; > + status = "disabled"; > + > + power-domains = <&rpmhpd SC7280_LCX>; > + power-domain-names = "lcx"; power-domain-names is not in the bindings. > + required-opps = <&rpmhpd_opp_nom>; > + > + clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, > + <&lpasscore LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, > + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, > + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, > + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, > + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, > + <&lpasscore LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, > + <&lpasscore LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, > + <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; > + clock-names = "aon_cc_audio_hm_h", > + "core_cc_sysnoc_mport_core", > + "audio_cc_codec_mem", > + "audio_cc_codec_mem0", > + "audio_cc_codec_mem1", > + "audio_cc_codec_mem2", > + "core_cc_ext_if0_ibit", > + "core_cc_ext_if1_ibit", > + "aon_cc_va_mem0"; Clocks do not match bindings. > + #sound-dai-cells = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > + > + interrupt-names = "lpass-irq-lpaif", > + "lpass-irq-vaif", > + "lpass-irq-rxtxif", > + "lpass-irq-hdmi"; interrupt-names ordering does not match bindings. -Doug
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 07f8b1e..4339483 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -271,6 +271,34 @@ modem-init; }; +&lpass_cpu { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&sec_mi2s_data0>, <&sec_mi2s_sclk>, <&sec_mi2s_ws>; + + mi2s-secondary@1 { + reg = <MI2S_SECONDARY>; + qcom,playback-sd-lines = <0>; + }; + + hdmi-primary@5 { + reg = <LPASS_DP_RX>; + }; + + wcd-rx@6 { + reg = <LPASS_CDC_DMA_RX0>; + }; + + wcd-tx@19 { + reg = <LPASS_CDC_DMA_TX3>; + }; + + va-tx@25 { + reg = <LPASS_CDC_DMA_VA_TX0>; + }; +}; + &pcie1 { status = "okay"; perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index daae5bc..2c90ed1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -18,6 +18,7 @@ #include <dt-bindings/reset/qcom,sdm845-aoss.h> #include <dt-bindings/reset/qcom,sdm845-pdc.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/sound/qcom,lpass.h> #include <dt-bindings/thermal/thermal.h> / { @@ -1750,6 +1751,64 @@ #clock-cells = <1>; }; + lpass_cpu: audio-subsystem@3260000 { + compatible = "qcom,sc7280-lpass-cpu"; + reg = <0 0x3260000 0 0xC000>, + <0 0x3280000 0 0x29000>, + <0 0x3340000 0 0x29000>, + <0 0x336C000 0 0x3000>, + <0 0x3987000 0 0x68000>, + <0 0x3B00000 0 0x29000>; + reg-names = "lpass-rxtx-cdc-dma-lpm", + "lpass-rxtx-lpaif", + "lpass-va-lpaif", + "lpass-va-cdc-dma-lpm", + "lpass-hdmiif", + "lpass-lpaif"; + + iommus = <&apps_smmu 0x1820 0>, + <&apps_smmu 0x1821 0>, + <&apps_smmu 0x1832 0>; + status = "disabled"; + + power-domains = <&rpmhpd SC7280_LCX>; + power-domain-names = "lcx"; + required-opps = <&rpmhpd_opp_nom>; + + clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, + <&lpasscore LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, + <&lpasscore LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, + <&lpasscore LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, + <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; + clock-names = "aon_cc_audio_hm_h", + "core_cc_sysnoc_mport_core", + "audio_cc_codec_mem", + "audio_cc_codec_mem0", + "audio_cc_codec_mem1", + "audio_cc_codec_mem2", + "core_cc_ext_if0_ibit", + "core_cc_ext_if1_ibit", + "aon_cc_va_mem0"; + + #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "lpass-irq-lpaif", + "lpass-irq-vaif", + "lpass-irq-rxtxif", + "lpass-irq-hdmi"; + }; + lpass_ag_noc: interconnect@3c40000 { reg = <0 0x03c40000 0 0xf080>; compatible = "qcom,sc7280-lpass-ag-noc";