| Message ID | 1645049106-30481-4-git-send-email-quic_khsieh@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm/dp: enable widebus feature base on chip hardware revision | expand |
On 17/02/2022 01:05, Kuogee Hsieh wrote: > To improve code readability, this patch replace BIT(x) with > correspond register bit define string > > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> This patch should come first. > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index b68e696..8f10aab 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -61,6 +61,12 @@ > > #define INTF_MUX 0x25C > > +#define INTF_CFG_ACTIVE_H_EN BIT(29) > +#define INTF_CFG_ACTIVE_V_EN BIT(30) > + > +#define INTF_CFG2_DATABUS_WIDEN BIT(0) > +#define INTF_CFG2_DATA_HCTL_EN BIT(4) > + > static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, > const struct dpu_mdss_cfg *m, > void __iomem *addr, > @@ -139,13 +145,13 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > > if (active_h_end) { > active_hctl = (active_h_end << 16) | active_h_start; > - intf_cfg |= BIT(29); > + intf_cfg |= INTF_CFG_ACTIVE_H_EN; > } else { > active_hctl = 0; > } > > if (active_v_end) > - intf_cfg |= BIT(30); > + intf_cfg |= INTF_CFG_ACTIVE_V_EN; > > hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; > display_hctl = (hsync_end_x << 16) | hsync_start_x; > @@ -156,7 +162,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > * if compression is enabled in 1 pixel per clock mode > */ > if (p->wide_bus_en) > - intf_cfg2 |= (BIT(0) | BIT(4)); > + intf_cfg2 |= (INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN); > > data_width = p->width; > > @@ -178,8 +184,8 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > active_hctl = (active_h_end << 16) | active_h_start; > display_hctl = active_hctl; > > - intf_cfg |= BIT(29); > - intf_cfg |= BIT(30); > + intf_cfg |= INTF_CFG_ACTIVE_H_EN; > + intf_cfg |= INTF_CFG_ACTIVE_V_EN; > } > > den_polarity = 0;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index b68e696..8f10aab 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -61,6 +61,12 @@ #define INTF_MUX 0x25C +#define INTF_CFG_ACTIVE_H_EN BIT(29) +#define INTF_CFG_ACTIVE_V_EN BIT(30) + +#define INTF_CFG2_DATABUS_WIDEN BIT(0) +#define INTF_CFG2_DATA_HCTL_EN BIT(4) + static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, const struct dpu_mdss_cfg *m, void __iomem *addr, @@ -139,13 +145,13 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, if (active_h_end) { active_hctl = (active_h_end << 16) | active_h_start; - intf_cfg |= BIT(29); + intf_cfg |= INTF_CFG_ACTIVE_H_EN; } else { active_hctl = 0; } if (active_v_end) - intf_cfg |= BIT(30); + intf_cfg |= INTF_CFG_ACTIVE_V_EN; hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; display_hctl = (hsync_end_x << 16) | hsync_start_x; @@ -156,7 +162,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, * if compression is enabled in 1 pixel per clock mode */ if (p->wide_bus_en) - intf_cfg2 |= (BIT(0) | BIT(4)); + intf_cfg2 |= (INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN); data_width = p->width; @@ -178,8 +184,8 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, active_hctl = (active_h_end << 16) | active_h_start; display_hctl = active_hctl; - intf_cfg |= BIT(29); - intf_cfg |= BIT(30); + intf_cfg |= INTF_CFG_ACTIVE_H_EN; + intf_cfg |= INTF_CFG_ACTIVE_V_EN; } den_polarity = 0;
To improve code readability, this patch replace BIT(x) with correspond register bit define string Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-)