Message ID | 26ebeebb59714dcce4a3ca8c80b4083d74a0b997.1645422822.git.ming.qian@nxp.com |
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State | Superseded |
Headers | show
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Mon, 21 Feb 2022 06:12:13 +0000 From: Ming Qian <ming.qian@nxp.com> To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v16 12/13] firmware: imx: scu-pd: imx8q: add vpu mu resources Date: Mon, 21 Feb 2022 14:10:31 +0800 Message-Id: <26ebeebb59714dcce4a3ca8c80b4083d74a0b997.1645422822.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <cover.1645422822.git.ming.qian@nxp.com> References: <cover.1645422822.git.ming.qian@nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SG2PR02CA0130.apcprd02.prod.outlook.com (2603:1096:4:188::8) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 28a48c6e-0433-489f-5640-08d9f5011a45 X-MS-TrafficTypeDiagnostic: PR3PR04MB7322:EE_ X-Microsoft-Antispam-PRVS: <PR3PR04MB73229345D8C11D4FFC33FEC7E73A9@PR3PR04MB7322.eurprd04.prod.outlook.com> X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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amphion video decoder/encoder driver
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diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index ff6569c4a53b..af3d057e6421 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -155,6 +155,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, + { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, + { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, + { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, + { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 }, /* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },