| Message ID | 1444208939-10233-5-git-send-email-gabriel.fernandez@linaro.org |
|---|---|
| State | Accepted |
| Commit | 848dd6a87a10bd24b5a4c8b84eaba3cdd0ec7a19 |
| Headers | show
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diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index 148e177..ae6d997 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -44,7 +44,7 @@ clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"; clocks = <&clk_sysin>;
Add support for new PLL-type for stih418 A9-PLL. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- arch/arm/boot/dts/stih418-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)