diff mbox series

drm/msm/adreno: fix cast in adreno_get_param()

Message ID 20220307133105.GA17534@kili
State Accepted
Commit aaa743d838da81ea173856c70caf96d8cdcbc320
Headers show
Series drm/msm/adreno: fix cast in adreno_get_param() | expand

Commit Message

Dan Carpenter March 7, 2022, 1:31 p.m. UTC
These casts need to happen before the shift.  The only time it would
matter would be if "rev.core" is >= 128.  In that case the sign bit
would be extended and we do not want that.

Fixes: afab9d91d872 ("drm/msm/adreno: Expose speedbin to userspace")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Akhil P Oommen March 7, 2022, 3:01 p.m. UTC | #1
On 3/7/2022 7:01 PM, Dan Carpenter wrote:
> These casts need to happen before the shift.  The only time it would
> matter would be if "rev.core" is >= 128.  In that case the sign bit
> would be extended and we do not want that.
>
> Fixes: afab9d91d872 ("drm/msm/adreno: Expose speedbin to userspace")
> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
> ---
>   drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 15c8997b7251..f7b3f6d266a9 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -244,10 +244,10 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
>   		*value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
>   		return 0;
>   	case MSM_PARAM_CHIP_ID:
> -		*value = (uint64_t) adreno_gpu->rev.patchid |
> -				(uint64_t) (adreno_gpu->rev.minor << 8) |
> -				(uint64_t) (adreno_gpu->rev.major << 16) |
> -				(uint64_t) (adreno_gpu->rev.core << 24);
> +		*value =  (uint64_t)adreno_gpu->rev.patchid |
> +			 ((uint64_t)adreno_gpu->rev.minor << 8) |
> +			 ((uint64_t)adreno_gpu->rev.major << 16) |
> +			 ((uint64_t)adreno_gpu->rev.core  << 24);
>   		if (!adreno_gpu->info->revn)
>   			*value |= ((uint64_t) adreno_gpu->speedbin) << 32;
>   		return 0;
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>

-Akhil
Stephen Boyd March 8, 2022, 8:25 p.m. UTC | #2
Quoting Dan Carpenter (2022-03-07 05:31:05)
> These casts need to happen before the shift.  The only time it would
> matter would be if "rev.core" is >= 128.  In that case the sign bit
> would be extended and we do not want that.
>
> Fixes: afab9d91d872 ("drm/msm/adreno: Expose speedbin to userspace")
> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 15c8997b7251..f7b3f6d266a9 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -244,10 +244,10 @@  int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
 		*value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
 		return 0;
 	case MSM_PARAM_CHIP_ID:
-		*value = (uint64_t) adreno_gpu->rev.patchid |
-				(uint64_t) (adreno_gpu->rev.minor << 8) |
-				(uint64_t) (adreno_gpu->rev.major << 16) |
-				(uint64_t) (adreno_gpu->rev.core << 24);
+		*value =  (uint64_t)adreno_gpu->rev.patchid |
+			 ((uint64_t)adreno_gpu->rev.minor << 8) |
+			 ((uint64_t)adreno_gpu->rev.major << 16) |
+			 ((uint64_t)adreno_gpu->rev.core  << 24);
 		if (!adreno_gpu->info->revn)
 			*value |= ((uint64_t) adreno_gpu->speedbin) << 32;
 		return 0;