diff mbox series

[v4,11/33] target/nios2: Use hw/registerfields.h for CR_STATUS fields

Message ID 20220308072005.307955-12-richard.henderson@linaro.org
State New
Headers show
Series target/nios2: Shadow register set, EIC and VIC | expand

Commit Message

Richard Henderson March 8, 2022, 7:19 a.m. UTC
Add all fields; retain the helper macros for single bit fields.
So far there are no uses of the multi-bit status fields.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/nios2/cpu.h | 27 ++++++++++++++++++---------
 1 file changed, 18 insertions(+), 9 deletions(-)

Comments

Peter Maydell March 8, 2022, 10:08 a.m. UTC | #1
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Add all fields; retain the helper macros for single bit fields.
> So far there are no uses of the multi-bit status fields.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/nios2/cpu.h | 27 ++++++++++++++++++---------
>  1 file changed, 18 insertions(+), 9 deletions(-)
>
> diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
> index 5bc0e353b4..26618baa70 100644
> --- a/target/nios2/cpu.h
> +++ b/target/nios2/cpu.h
> @@ -23,6 +23,7 @@
>
>  #include "exec/cpu-defs.h"
>  #include "hw/core/cpu.h"
> +#include "hw/registerfields.h"
>  #include "qom/object.h"
>
>  typedef struct CPUNios2State CPUNios2State;
> @@ -80,15 +81,23 @@ struct Nios2CPUClass {
>
>  /* Control register aliases */
>  #define CR_STATUS        0
> -#define   CR_STATUS_PIE  (1 << 0)
> -#define   CR_STATUS_U    (1 << 1)
> -#define   CR_STATUS_EH   (1 << 2)
> -#define   CR_STATUS_IH   (1 << 3)
> -#define   CR_STATUS_IL   (63 << 4)
> -#define   CR_STATUS_CRS  (63 << 10)
> -#define   CR_STATUS_PRS  (63 << 16)
> -#define   CR_STATUS_NMI  (1 << 22)
> -#define   CR_STATUS_RSIE (1 << 23)
> +
> +FIELD(CR_STATUS, PIE, 0, 1)
> +FIELD(CR_STATUS, U, 1, 1)
> +FIELD(CR_STATUS, EH, 2, 1)
> +FIELD(CR_STATUS, IH, 3, 1)
> +FIELD(CR_STATUS, IL, 4, 6)
> +FIELD(CR_STATUS, CRS, 10, 6)
> +FIELD(CR_STATUS, PRS, 16, 6)
> +FIELD(CR_STATUS, NMI, 22, 1)
> +
> +#define CR_STATUS_PIE  (1u << R_CR_STATUS_PIE_SHIFT)
> +#define CR_STATUS_U    (1u << R_CR_STATUS_U_SHIFT)
> +#define CR_STATUS_EH   (1u << R_CR_STATUS_EH_SHIFT)
> +#define CR_STATUS_IH   (1u << R_CR_STATUS_IH_SHIFT)
> +#define CR_STATUS_NMI  (1u << R_CR_STATUS_NMI_SHIFT)
> +#define CR_STATUS_RSIE (1u << R_CR_STATUS_RSIE_SHIFT)

Since these are all 1 bit fields you can use
#define CR_STATUS_PIE R_CR_STATUS_PIE_MASK
etc rather than manually shifting by the shift count.

-- PMM
Richard Henderson March 8, 2022, 7:34 p.m. UTC | #2
On 3/8/22 00:08, Peter Maydell wrote:
>> +#define CR_STATUS_RSIE (1u << R_CR_STATUS_RSIE_SHIFT)
> 
> Since these are all 1 bit fields you can use
> #define CR_STATUS_PIE R_CR_STATUS_PIE_MASK
> etc rather than manually shifting by the shift count.

Quite right, thanks.

r~
diff mbox series

Patch

diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 5bc0e353b4..26618baa70 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -23,6 +23,7 @@ 
 
 #include "exec/cpu-defs.h"
 #include "hw/core/cpu.h"
+#include "hw/registerfields.h"
 #include "qom/object.h"
 
 typedef struct CPUNios2State CPUNios2State;
@@ -80,15 +81,23 @@  struct Nios2CPUClass {
 
 /* Control register aliases */
 #define CR_STATUS        0
-#define   CR_STATUS_PIE  (1 << 0)
-#define   CR_STATUS_U    (1 << 1)
-#define   CR_STATUS_EH   (1 << 2)
-#define   CR_STATUS_IH   (1 << 3)
-#define   CR_STATUS_IL   (63 << 4)
-#define   CR_STATUS_CRS  (63 << 10)
-#define   CR_STATUS_PRS  (63 << 16)
-#define   CR_STATUS_NMI  (1 << 22)
-#define   CR_STATUS_RSIE (1 << 23)
+
+FIELD(CR_STATUS, PIE, 0, 1)
+FIELD(CR_STATUS, U, 1, 1)
+FIELD(CR_STATUS, EH, 2, 1)
+FIELD(CR_STATUS, IH, 3, 1)
+FIELD(CR_STATUS, IL, 4, 6)
+FIELD(CR_STATUS, CRS, 10, 6)
+FIELD(CR_STATUS, PRS, 16, 6)
+FIELD(CR_STATUS, NMI, 22, 1)
+
+#define CR_STATUS_PIE  (1u << R_CR_STATUS_PIE_SHIFT)
+#define CR_STATUS_U    (1u << R_CR_STATUS_U_SHIFT)
+#define CR_STATUS_EH   (1u << R_CR_STATUS_EH_SHIFT)
+#define CR_STATUS_IH   (1u << R_CR_STATUS_IH_SHIFT)
+#define CR_STATUS_NMI  (1u << R_CR_STATUS_NMI_SHIFT)
+#define CR_STATUS_RSIE (1u << R_CR_STATUS_RSIE_SHIFT)
+
 #define CR_ESTATUS       1
 #define CR_BSTATUS       2
 #define CR_IENABLE       3