diff mbox series

[v4,18/33] target/nios2: Implement cpuid

Message ID 20220308072005.307955-19-richard.henderson@linaro.org
State New
Headers show
Series target/nios2: Shadow register set, EIC and VIC | expand

Commit Message

Richard Henderson March 8, 2022, 7:19 a.m. UTC 
Copy the existing cpu_index into the space reserved for CR_CPUID.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/nios2/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Peter Maydell March 8, 2022, 10:52 a.m. UTC | #1 
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Copy the existing cpu_index into the space reserved for CR_CPUID.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/nios2/cpu.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
> index 189adf111c..fbcb4da737 100644
> --- a/target/nios2/cpu.c
> +++ b/target/nios2/cpu.c
> @@ -159,6 +159,7 @@ static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model)
>  static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
>  {
>      CPUState *cs = CPU(dev);
> +    Nios2CPU *cpu = NIOS2_CPU(cs);
>      Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
>      Error *local_err = NULL;
>
> @@ -171,6 +172,9 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
>      qemu_init_vcpu(cs);
>      cpu_reset(cs);
>
> +    /* We have reserved storage for ctrl[CR_CPUID]; might as well use it. */
> +    cpu->env.cpuid = cs->cpu_index;
> +
>      ncc->parent_realize(dev, errp);
>  }

I guess. This will have no effect as all our nios2 boards are
single-CPU.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM
Richard Henderson March 8, 2022, 7:50 p.m. UTC | #2 
On 3/8/22 00:52, Peter Maydell wrote:
> I guess. This will have no effect as all our nios2 boards are
> single-CPU.
> 
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Oh, fair enough.  I didn't even think of that (even though I've just spent quite a bit of 
time on interrupts, and there's no sign of an inter-processor interrupt).


r~
diff mbox series

Patch

diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 189adf111c..fbcb4da737 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -159,6 +159,7 @@  static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model)
 static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);
+    Nios2CPU *cpu = NIOS2_CPU(cs);
     Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
     Error *local_err = NULL;
 
@@ -171,6 +172,9 @@  static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
     qemu_init_vcpu(cs);
     cpu_reset(cs);
 
+    /* We have reserved storage for ctrl[CR_CPUID]; might as well use it. */
+    cpu->env.cpuid = cs->cpu_index;
+
     ncc->parent_realize(dev, errp);
 }