@@ -96,6 +96,9 @@ static acpi_status tb_acpi_add_link(acpi_handle handle, u32 level, void *data,
dev_name(&pdev->dev));
}
+ pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY);
+ pm_runtime_use_autosuspend(&pdev->dev);
+ pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put(&pdev->dev);
}
@@ -1066,6 +1066,7 @@ static int tb_tunnel_pci(struct tb *tb, struct tb_switch *sw)
struct tb_cm *tcm = tb_priv(tb);
struct tb_switch *parent_sw;
struct tb_tunnel *tunnel;
+ struct device_link *link;
up = tb_switch_find_port(sw, TB_TYPE_PCIE_UP);
if (!up)
@@ -1099,6 +1100,16 @@ static int tb_tunnel_pci(struct tb *tb, struct tb_switch *sw)
if (tb_switch_pcie_l1_enable(sw))
tb_sw_warn(sw, "failed to enable PCIe L1 for Titan Ridge\n");
+ list_for_each_entry(link, &tb->nhi->pdev->dev.links.consumers, s_node) {
+ if (pci_pcie_type(to_pci_dev(link->consumer)) == PCI_EXP_TYPE_ROOT_PORT) {
+ if (pm_runtime_status_suspended(link->consumer)) {
+ pm_runtime_get_sync(link->consumer);
+ pm_runtime_mark_last_busy(link->consumer);
+ pm_runtime_put_sync_autosuspend(link->consumer);
+ }
+ }
+ }
+
list_add_tail(&tunnel->list, &tcm->tunnel_list);
return 0;
}