| Message ID | 20220315152717.20045-1-biju.das.jz@bp.renesas.com |
|---|---|
| State | Accepted |
| Commit | 74273035c7e486fa046ee7f80fbdb9c19169ef19 |
| Headers | show |
| Series | [1/2] dt-bindings: pinctrl: renesas: Document RZ/G2UL pinctrl | expand |
Hi Biju, On Tue, Mar 15, 2022 at 4:27 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Document Renesas RZ/G2UL pinctrl bindings. RZ/G2UL GPIO block is > almost identical to RZ/G2L and has lesser pins compared to RZ/G2L. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > @@ -21,6 +21,10 @@ description: > properties: > compatible: > oneOf: > + - items: > + - enum: > + - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} This can be combined with the enum below. > + > - items: > - enum: > - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-pinctrl-for-v5.19, with the above fixed. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 08ea34f39574..71057e570e49 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -11,8 +11,8 @@ maintainers: - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> description: - The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO - controller. + The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and + GPIO controller. Pin multiplexing and GPIO configuration is performed on a per-pin basis. Each port features up to 8 pins, each of them configurable for GPIO function (port mode) or in alternate function mode. @@ -21,6 +21,10 @@ description: properties: compatible: oneOf: + - items: + - enum: + - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} + - items: - enum: - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}