| Message ID | 562F8257.6080006@arm.com |
|---|---|
| State | Accepted |
| Commit | 6a9ee02f7afa32a1bded5d4d0644ac1b02064148 |
| Headers | show |
Ping. https://gcc.gnu.org/ml/gcc-patches/2015-10/msg02898.html Thanks, Kyrill On 27/10/15 13:55, Kyrill Tkachov wrote: > Hi all, > > This patch allows us to handle the *combine_vcvtf2i pattern in rtx costs by properly identifying it > as a toint coversion. Before this I saw a pattern like: > (set (reg/i:SI 0 r0) > (fix:SI (fix:SF (mult:SF (reg:SF 16 s0 [ a ]) > (const_double:SF 3.2e+1 [0x0.8p+6]))))) > > being assigned a cost of 40 because the costs blindly recursed into the operands. > With this patch for -mcpu=cortex-a57 I see it being assigned a cost of 4. > > Bootstrapped and tested on arm-none-linux-gnueabihf. > > Ok for trunk? > > Thanks, > Kyrill > > 2015-10-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com> > > * config/arm/arm.c (arm_new_rtx_costs, FIX case): Handle > combine_vcvtf2i pattern.
commit 1e040710d1022ce816eac9b4f6065bc7aa2be9cf
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Wed Oct 14 11:26:07 2015 +0100
[ARM] Fix costing of vmul+vcvt combine pattern
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index b37b507..33ad433 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -11064,6 +11064,23 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
case UNSIGNED_FIX:
if (TARGET_HARD_FLOAT)
{
+ /* The *combine_vcvtf2i reduces a vmul+vcvt into
+ a vcvt fixed-point conversion. */
+ if (code == FIX && mode == SImode
+ && GET_CODE (XEXP (x, 0)) == FIX
+ && GET_MODE (XEXP (x, 0)) == SFmode
+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
+ && vfp3_const_double_for_bits (XEXP (XEXP (XEXP (x, 0), 0), 1))
+ > 0)
+ {
+ if (speed_p)
+ *cost += extra_cost->fp[0].toint;
+
+ *cost += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0), mode,
+ code, 0, speed_p);
+ return true;
+ }
+
if (GET_MODE_CLASS (mode) == MODE_INT)
{
mode = GET_MODE (XEXP (x, 0));
Hi all, This patch allows us to handle the *combine_vcvtf2i pattern in rtx costs by properly identifying it as a toint coversion. Before this I saw a pattern like: (set (reg/i:SI 0 r0) (fix:SI (fix:SF (mult:SF (reg:SF 16 s0 [ a ]) (const_double:SF 3.2e+1 [0x0.8p+6]))))) being assigned a cost of 40 because the costs blindly recursed into the operands. With this patch for -mcpu=cortex-a57 I see it being assigned a cost of 4. Bootstrapped and tested on arm-none-linux-gnueabihf. Ok for trunk? Thanks, Kyrill 2015-10-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/arm/arm.c (arm_new_rtx_costs, FIX case): Handle combine_vcvtf2i pattern.