| Message ID | 1649157167-29106-3-git-send-email-quic_srivasam@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add lpass pin control support for audio on sc7280 based targets | expand |
On 4/6/2022 7:45 AM, Matthias Kaehlcke wrote: Thanks Matthias for your time and Valuable inputs!!! > On Tue, Apr 05, 2022 at 10:14:20AM -0700, Matthias Kaehlcke wrote: >> On Tue, Apr 05, 2022 at 04:42:47PM +0530, Srinivasa Rao Mandadapu wrote: >>> Add LPASS LPI pinctrl node required for Audio functionality on sc7280 >>> based platforms. >>> >>> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> >>> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> >>> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 98 ++++++++++++++++++++++++++++ >>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 107 +++++++++++++++++++++++++++++++ >>> 2 files changed, 205 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >>> index 2afbbe3..f912a89 100644 >>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >>> @@ -238,6 +238,104 @@ >>> modem-init; >>> }; >>> >>> +&lpass_tlmm { >>> + dmic01_active: dmic01-active { >>> + clk { >>> + drive-strength = <8>; >>> + }; >>> + >>> + data { >>> + drive-strength = <8>; >> The DMIC data pins are input pins, right? Why does an input pin need a drive >> strength? Same for other input pins. Okay. Will remove this. >> >>> + }; >>> + }; >> There's no need to reference 'lpass_tlmm' nor to repeat $label: $node. >> Instead just use phandles: Okay. Will change accordingly. >> >> &dmic01_active { >> clk { >> drive-strength = <8>; >> }; >> >> data { >> drive-strength = <8>; >> }; >> }; >> >> Rather than replicating the node hierarchy you could also just give each pin a >> label, and then: >> >> &dmic01_clk_active { >> drive-strength = <8>; >> }; >> >> &dmic01_data_active { >> drive-strength = <8>; >> }; >> >> I don't have a strong preference, but wonder if the grouping adds any value. > One more thing: please also drop the '_active' suffix, it is not needed. With > that I think it's clearer to get rid of the grouping. For now will continue as it's. Anyway we are removing dmic01_data_active. > >>> + >>> + dmic01_sleep: dmic01-sleep { >>> + clk { >>> + drive-strength = <2>; >>> + bias-disable; >>> + }; >>> + >>> + data { >>> + drive-strength = <2>; >>> + pull-down; >>> + }; >>> + }; >>> + >>> + dmic23_active: dmic02-active { >>> + clk { >>> + drive-strength = <8>; >>> + }; >>> + >>> + data { >>> + drive-strength = <8>; >>> + }; >>> + }; >>> + >>> + dmic23_sleep: dmic02-sleep { >>> + clk { >>> + drive-strength = <2>; >>> + bias-disable; >>> + }; >>> + >>> + data { >>> + drive-strength = <2>; >>> + pull-down; >>> + }; >>> + }; >>> + >>> + rx_swr_active: rx-swr-active { >>> + clk { >>> + drive-strength = <2>; >>> + slew-rate = <1>; >>> + bias-disable; >>> + }; >>> + >>> + data { >>> + drive-strength = <2>; >>> + slew-rate = <1>; >>> + bias-bus-hold; >>> + }; >>> + }; >>> + >>> + rx_swr_sleep: rx-swr-sleep { >>> + clk { >>> + drive-strength = <2>; >>> + bias-pull-down; >>> + }; >>> + >>> + data { >>> + drive-strength = <2>; >>> + bias-pull-down; >>> + }; >>> + }; >>> + >>> + tx_swr_active: tx-swr-active { >>> + clk { >>> + drive-strength = <2>; >>> + slew-rate = <1>; >>> + bias-disable; >>> + }; >>> + >>> + data { >>> + drive-strength = <2>; >>> + slew-rate = <1>; >>> + bias-bus-hold; >>> + }; >>> + }; >>> + >>> + tx_swr_sleep: tx-swr-sleep { >>> + clk { >>> + drive-strength = <2>; >>> + bias-pull-down; >>> + }; >>> + >>> + data { >>> + drive-strength = <2>; >>> + bias-bus-hold; >>> + }; >>> + }; >>> +}; >>> + >>> &pcie1 { >>> status = "okay"; >>> perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>; >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> index 8d8cec5..db74fc3 100644 >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> @@ -1987,6 +1987,113 @@ >>> qcom,bcm-voters = <&apps_bcm_voter>; >>> }; >>> >>> + lpass_tlmm: pinctrl@33c0000 { >>> + compatible = "qcom,sc7280-lpass-lpi-pinctrl"; >>> + reg = <0 0x33c0000 0x0 0x20000>, >>> + <0 0x3550000 0x0 0x10000>; >> Pad addresses to 8 digits. Okay. >> >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + gpio-ranges = <&lpass_tlmm 0 0 15>; >>> + >>> + #clock-cells = <1>; >>> + >>> + dmic01_active: dmic01-active { >>> + clk { >>> + pins = "gpio6"; >>> + function = "dmic1_clk"; >>> + }; >>> + >>> + data { >>> + pins = "gpio7"; >>> + function = "dmic1_data"; >>> + }; >>> + }; >>> + >>> + dmic01_sleep: dmic01-sleep { >>> + clk { >>> + pins = "gpio6"; >>> + function = "dmic1_clk"; >>> + }; >>> + >>> + data { >>> + pins = "gpio7"; >>> + function = "dmic1_data"; >>> + }; >>> + }; >>> + >>> + dmic23_active: dmic02-active { >> is it intentional that the node name is 'dmic02*', but the label 'dmic23*'? typo error. will fix it. >> >>> + clk { >>> + pins = "gpio8"; >>> + function = "dmic2_clk"; >>> + }; >>> + >>> + data { >>> + pins = "gpio9"; >>> + function = "dmic2_data"; >>> + }; >>> + }; >>> + >>> + dmic23_sleep: dmic02-sleep { >> ditto Okay. >> >>> + clk { >>> + pins = "gpio8"; >>> + function = "dmic2_clk"; >>> + }; >>> + >>> + data { >>> + pins = "gpio9"; >>> + function = "dmic2_data"; >>> + }; >>> + }; >>> + >>> + rx_swr_active: rx-swr-active { >>> + clk { >>> + pins = "gpio3"; >>> + function = "swr_rx_clk"; >>> + }; >>> + >>> + data { >>> + pins = "gpio4", "gpio5"; >>> + function = "swr_rx_data"; >>> + }; >>> + }; >>> + >>> + rx_swr_sleep: rx-swr-sleep { >>> + clk { >>> + pins = "gpio3"; >>> + function = "swr_rx_clk"; >>> + }; >>> + >>> + data { >>> + pins = "gpio4", "gpio5"; >>> + function = "swr_rx_data"; >>> + }; >>> + }; >>> + >>> + tx_swr_active: tx-swr-active { >>> + clk { >>> + pins = "gpio0"; >>> + function = "swr_tx_clk"; >>> + }; >>> + >>> + data { >>> + pins = "gpio1", "gpio2", "gpio14"; >>> + function = "swr_tx_data"; >>> + }; >>> + }; >>> + >>> + tx_swr_sleep: tx-swr-sleep { >>> + clk { >>> + pins = "gpio0"; >>> + function = "swr_tx_clk"; >>> + }; >>> + >>> + data { >>> + pins = "gpio1", "gpio2", "gpio14"; >>> + function = "swr_tx_data"; >>> + }; >>> + }; >>> + }; >>> + >>> gpu: gpu@3d00000 { >>> compatible = "qcom,adreno-635.0", "qcom,adreno"; >>> reg = <0 0x03d00000 0 0x40000>,
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 2afbbe3..f912a89 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -238,6 +238,104 @@ modem-init; }; +&lpass_tlmm { + dmic01_active: dmic01-active { + clk { + drive-strength = <8>; + }; + + data { + drive-strength = <8>; + }; + }; + + dmic01_sleep: dmic01-sleep { + clk { + drive-strength = <2>; + bias-disable; + }; + + data { + drive-strength = <2>; + pull-down; + }; + }; + + dmic23_active: dmic02-active { + clk { + drive-strength = <8>; + }; + + data { + drive-strength = <8>; + }; + }; + + dmic23_sleep: dmic02-sleep { + clk { + drive-strength = <2>; + bias-disable; + }; + + data { + drive-strength = <2>; + pull-down; + }; + }; + + rx_swr_active: rx-swr-active { + clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_sleep: rx-swr-sleep { + clk { + drive-strength = <2>; + bias-pull-down; + }; + + data { + drive-strength = <2>; + bias-pull-down; + }; + }; + + tx_swr_active: tx-swr-active { + clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + tx_swr_sleep: tx-swr-sleep { + clk { + drive-strength = <2>; + bias-pull-down; + }; + + data { + drive-strength = <2>; + bias-bus-hold; + }; + }; +}; + &pcie1 { status = "okay"; perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 8d8cec5..db74fc3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1987,6 +1987,113 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sc7280-lpass-lpi-pinctrl"; + reg = <0 0x33c0000 0x0 0x20000>, + <0 0x3550000 0x0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + + #clock-cells = <1>; + + dmic01_active: dmic01-active { + clk { + pins = "gpio6"; + function = "dmic1_clk"; + }; + + data { + pins = "gpio7"; + function = "dmic1_data"; + }; + }; + + dmic01_sleep: dmic01-sleep { + clk { + pins = "gpio6"; + function = "dmic1_clk"; + }; + + data { + pins = "gpio7"; + function = "dmic1_data"; + }; + }; + + dmic23_active: dmic02-active { + clk { + pins = "gpio8"; + function = "dmic2_clk"; + }; + + data { + pins = "gpio9"; + function = "dmic2_data"; + }; + }; + + dmic23_sleep: dmic02-sleep { + clk { + pins = "gpio8"; + function = "dmic2_clk"; + }; + + data { + pins = "gpio9"; + function = "dmic2_data"; + }; + }; + + rx_swr_active: rx-swr-active { + clk { + pins = "gpio3"; + function = "swr_rx_clk"; + }; + + data { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + }; + }; + + rx_swr_sleep: rx-swr-sleep { + clk { + pins = "gpio3"; + function = "swr_rx_clk"; + }; + + data { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + }; + }; + + tx_swr_active: tx-swr-active { + clk { + pins = "gpio0"; + function = "swr_tx_clk"; + }; + + data { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + }; + }; + + tx_swr_sleep: tx-swr-sleep { + clk { + pins = "gpio0"; + function = "swr_tx_clk"; + }; + + data { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + }; + }; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-635.0", "qcom,adreno"; reg = <0 0x03d00000 0 0x40000>,