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[02/41] hw/intc/arm_gicv3: Sanity-check num-cpu property

Message ID 20220408141550.1271295-3-peter.maydell@linaro.org
State Superseded
Headers show
Series arm: Implement GICv4 | expand

Commit Message

Peter Maydell April 8, 2022, 2:15 p.m. UTC 
In the GICv3 code we implicitly rely on there being at least one CPU
and thus at least one redistributor and CPU interface.  Sanity-check
that the property the board code sets is not zero.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Doing this would be a board code error, but we might as well
get a clean diagnostic for it and not have to think about
num_cpu == 0 as a special case later.
---
 hw/intc/arm_gicv3_common.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Richard Henderson April 8, 2022, 11:17 p.m. UTC | #1 
On 4/8/22 07:15, Peter Maydell wrote:
> In the GICv3 code we implicitly rely on there being at least one CPU
> and thus at least one redistributor and CPU interface.  Sanity-check
> that the property the board code sets is not zero.
> 
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> Doing this would be a board code error, but we might as well
> get a clean diagnostic for it and not have to think about
> num_cpu == 0 as a special case later.
> ---
>   hw/intc/arm_gicv3_common.c | 4 ++++
>   1 file changed, 4 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 4ca5ae9bc56..90204be25b6 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -328,6 +328,10 @@  static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
                    s->num_irq, GIC_INTERNAL);
         return;
     }
+    if (s->num_cpu == 0) {
+        error_setg(errp, "num-cpu must be at least 1");
+        return;
+    }
 
     /* ITLinesNumber is represented as (N / 32) - 1, so this is an
      * implementation imposed restriction, not an architectural one,