| Message ID | 20220410055725.380246-6-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: More trivial features, A76, N1 | expand |
On Sun, 10 Apr 2022 at 07:07, Richard Henderson <richard.henderson@linaro.org> wrote: > > This extension concerns not merging memory access, which TCG does > not implement. Thus we can trivially enable this feature. > Add a comment to handle_hint for the DGH instruction, but no code. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a0429538cc..199ca437a0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -795,6 +795,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 = t; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cc54dff83c..c3c1a19dea 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1442,6 +1442,7 @@ static void handle_hint(DisasContext *s, uint32_t insn, break; case 0b00100: /* SEV */ case 0b00101: /* SEVL */ + case 0b00110: /* DGH */ /* we treat all as NOP at least for now */ break; case 0b00111: /* XPACLRI */
This extension concerns not merging memory access, which TCG does not implement. Thus we can trivially enable this feature. Add a comment to handle_hint for the DGH instruction, but no code. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 1 + 2 files changed, 2 insertions(+)