@@ -76,6 +76,7 @@ Optional Properties:
"cpu-sdhc".
Please refer to Documentation/devicetree/bindings/
interconnect/ for more details.
+- resets: Phandle and reset specifier for the device's reset.
Example:
@@ -98,6 +99,8 @@ Example:
<&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
+ resets = <&gcc GCC_SDCC1_BCR>;
+
qcom,dll-config = <0x000f642c>;
qcom,ddr-config = <0x80040868>;
};
@@ -118,6 +121,8 @@ Example:
clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
+ resets = <&gcc GCC_SDCC2_BCR>;
+
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
};
Add gcc hardware reset supported strings for qcom-sdhci controller. Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com> --- Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 5 +++++ 1 file changed, 5 insertions(+)