diff mbox series

[PULL,12/54] target/arm: Use tcg_constant in disas_movw_imm

Message ID	20220428143958.2451229-13-peter.maydell@linaro.org
State	Accepted
Commit	12f1d809e6c0c6ef2466a2629d71e68549dd545e
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 12/54] target/arm: Use tcg_constant in disas_movw_imm Date: Thu, 28 Apr 2022 15:39:16 +0100 Message-Id: <20220428143958.2451229-13-peter.maydell@linaro.org> In-Reply-To: <20220428143958.2451229-1-peter.maydell@linaro.org> References: <20220428143958.2451229-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	[PULL,01/54] target/arm: Use tcg_constant in gen_probe_access \| expand [PULL,01/54] target/arm: Use tcg_constant in gen_probe_access [PULL,02/54] target/arm: Use tcg_constant in gen_mte_check* [PULL,03/54] target/arm: Use tcg_constant in gen_exception* [PULL,04/54] target/arm: Use tcg_constant in gen_adc_CC [PULL,05/54] target/arm: Use tcg_constant in handle_msr_i [PULL,06/54] target/arm: Use tcg_constant in handle_sys [PULL,07/54] target/arm: Use tcg_constant in disas_exc [PULL,08/54] target/arm: Use tcg_constant in gen_compare_and_swap_pair [PULL,09/54] target/arm: Use tcg_constant in disas_ld_lit [PULL,10/54] target/arm: Use tcg_constant in disas_ldst_* [PULL,11/54] target/arm: Use tcg_constant in disas_add_sum_imm* [PULL,12/54] target/arm: Use tcg_constant in disas_movw_imm [PULL,13/54] target/arm: Use tcg_constant in shift_reg_imm [PULL,14/54] target/arm: Use tcg_constant in disas_cond_select [PULL,15/54] target/arm: Use tcg_constant in handle_{rev16,crc32} [PULL,16/54] target/arm: Use tcg_constant in disas_data_proc_2src [PULL,17/54] target/arm: Use tcg_constant in disas_fp* [PULL,18/54] target/arm: Use tcg_constant in simd shift expanders [PULL,19/54] target/arm: Use tcg_constant in simd fp/int conversion [PULL,20/54] target/arm: Use tcg_constant in 2misc expanders [PULL,21/54] target/arm: Use tcg_constant in balance of translate-a64.c [PULL,22/54] target/arm: Use tcg_constant for aa32 exceptions [PULL,23/54] target/arm: Use tcg_constant for disas_iwmmxt_insn [PULL,24/54] target/arm: Use tcg_constant for gen_{msr,mrs} [PULL,25/54] target/arm: Use tcg_constant for vector shift expanders [PULL,26/54] target/arm: Use tcg_constant for do_coproc_insn [PULL,27/54] target/arm: Use tcg_constant for gen_srs [PULL,28/54] target/arm: Use tcg_constant for op_s_{rri,rxi}_rot [PULL,29/54] target/arm: Use tcg_constant for MOVW, UMAAL, CRC32 [PULL,30/54] target/arm: Use tcg_constant for v7m MRS, MSR [PULL,31/54] target/arm: Use tcg_constant for TT, SAT, SMMLA [PULL,32/54] target/arm: Use tcg_constant in LDM, STM [PULL,33/54] target/arm: Use tcg_constant in CLRM, DLS, WLS, LE [PULL,34/54] target/arm: Use tcg_constant in trans_CPS_v7m [PULL,35/54] target/arm: Use tcg_constant in trans_CSEL [PULL,36/54] target/arm: Use tcg_constant for trans_INDEX_* [PULL,37/54] target/arm: Use tcg_constant in SINCDEC, INCDEC [PULL,38/54] target/arm: Use tcg_constant in FCPY, CPY [PULL,39/54] target/arm: Use tcg_constant in {incr, wrap}_last_active [PULL,40/54] target/arm: Use tcg_constant in do_clast_scalar [PULL,41/54] target/arm: Use tcg_constant in WHILE [PULL,42/54] target/arm: Use tcg_constant in LD1, ST1 [PULL,43/54] target/arm: Use tcg_constant in SUBR [PULL,44/54] target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm [PULL,45/54] target/arm: Use tcg_constant for predicate descriptors [PULL,46/54] target/arm: Use tcg_constant for do_brk{2,3} [PULL,47/54] target/arm: Use tcg_constant for vector descriptor [PULL,48/54] target/arm: Disable cryptographic instructions when neon is disabled [PULL,49/54] target/arm: Use field names for accessing DBGWCRn [PULL,50/54] hw/arm/smmuv3: Cache event fault record [PULL,51/54] hw/arm/smmuv3: Add space in guest error message [PULL,52/54] target/arm: Advertise support for FEAT_TTL [PULL,53/54] target/arm: Advertise support for FEAT_BBM level 2 [PULL,54/54] hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2

Commit Message

Peter Maydell April 28, 2022, 2:39 p.m. UTC

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff mbox series

Patch

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 6c88772eb32..537eebbf1da 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -4419,7 +4419,6 @@  static void disas_movw_imm(DisasContext *s, uint32_t insn)
     int opc = extract32(insn, 29, 2);
     int pos = extract32(insn, 21, 2) << 4;
     TCGv_i64 tcg_rd = cpu_reg(s, rd);
-    TCGv_i64 tcg_imm;
 
     if (!sf && (pos >= 32)) {
         unallocated_encoding(s);
@@ -4439,9 +4438,7 @@  static void disas_movw_imm(DisasContext *s, uint32_t insn)
         tcg_gen_movi_i64(tcg_rd, imm);
         break;
     case 3: /* MOVK */
-        tcg_imm = tcg_const_i64(imm);
-        tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
-        tcg_temp_free_i64(tcg_imm);
+        tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_constant_i64(imm), pos, 16);
         if (!sf) {
             tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
         }