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[v2,1/3] dt-bindings: misc: add bindings for Intel HPS Copy Engine

Message ID 20220503194546.1287679-2-matthew.gerlach@linux.intel.com
State Superseded
Headers show
Series Add device tree for Intel n6000 | expand

Commit Message

matthew.gerlach@linux.intel.com May 3, 2022, 7:45 p.m. UTC 
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

Add device tree bindings documentation for the Intel Hard
Processor System (HPS) Copy Engine.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
 .../bindings/misc/intel,hps-copy-engine.yaml  | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/intel,hps-copy-engine.yaml
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Patch

diff --git a/Documentation/devicetree/bindings/misc/intel,hps-copy-engine.yaml b/Documentation/devicetree/bindings/misc/intel,hps-copy-engine.yaml
new file mode 100644
index 000000000000..74e7da9002f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,hps-copy-engine.yaml
@@ -0,0 +1,48 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2022, Intel Corporation
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/misc/intel,hps-copy-engine.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel HPS Copy Engine
+
+maintainers:
+  - Matthew Gerlach <matthew.gerlach@linux.intel.com>
+
+description: |
+  The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy
+  a bootable image from host memory to HPS DDR.  Additionally, there is a
+  register the HPS can use to indicate the state of booting the copied image as
+  well as a keep-a-live indication to the host.
+
+properties:
+  compatible:
+    items:
+      - const: intel,hps-copy-engine
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    agilex_hps_bridges: bus@80000000 {
+        compatible = "simple-bus";
+        reg = <0x80000000 0x60000000>,
+              <0xf9000000 0x00100000>;
+        reg-names = "axi_h2f", "axi_h2f_lw";
+        #address-cells = <0x2>;
+        #size-cells = <0x1>;
+        ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
+
+        hps_cp_eng@0 {
+            compatible = "intel,hps-copy-engine";
+            reg = <0x00000000 0x00000000 0x00001000>;
+        };
+    };