| Message ID | 20220505161425.1.Icf6f3796d2fa122b4c0566d9317b461bfbc24b7f@changeid |
|---|---|
| State | Accepted |
| Commit | d756a0b29f4013badc9d3b4ee7c24d4a700cbac9 |
| Headers | show |
| Series | arm64: dts: qcom: sc7280: Set SPI flash to 50 MHz for herobrine boards | expand |
On Thu, May 05, 2022 at 04:14:30PM -0700, Douglas Anderson wrote: > sc7280-herobrine based boards are specced to be able to access their > SPI flash at 50 MHz with the drive strength of the pins set at 8. The > drive strength is already set to 8 in "sc7280-herobrine.dtsi", so > let's bump up the clock. The matching firmware change for this is at: > > https://review.coreboot.org/c/coreboot/+/63948 > > NOTE: the firmware change isn't _required_ to make the kernel work at > 50 MHz, it merely shows that the boards are known to work fine at 50 > MHz. > > ALSO NOTE: this doesn't update the "sc7280-chrome-common.dtsi" file > which is used by both herobrine boards and IDP. At the moment the IDP > boards aren't configuring a drive strength of 8 and it seems safer to > just leave them at the slower speed if they're already working. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
On Thu, 5 May 2022 16:14:30 -0700, Douglas Anderson wrote: > sc7280-herobrine based boards are specced to be able to access their > SPI flash at 50 MHz with the drive strength of the pins set at 8. The > drive strength is already set to 8 in "sc7280-herobrine.dtsi", so > let's bump up the clock. The matching firmware change for this is at: > > https://review.coreboot.org/c/coreboot/+/63948 > > [...] Applied, thanks! [1/1] arm64: dts: qcom: sc7280: Set SPI flash to 50 MHz for herobrine boards commit: d756a0b29f4013badc9d3b4ee7c24d4a700cbac9 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index d58045dd7334..939d9e922834 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -452,6 +452,10 @@ &sdhc_2 { cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; }; +&spi_flash { + spi-max-frequency = <50000000>; +}; + /* Fingerprint, enabled on a per-board basis */ ap_spi_fp: &spi9 { pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs_gpio_init_high>, <&qup_spi9_cs_gpio>;
sc7280-herobrine based boards are specced to be able to access their SPI flash at 50 MHz with the drive strength of the pins set at 8. The drive strength is already set to 8 in "sc7280-herobrine.dtsi", so let's bump up the clock. The matching firmware change for this is at: https://review.coreboot.org/c/coreboot/+/63948 NOTE: the firmware change isn't _required_ to make the kernel work at 50 MHz, it merely shows that the boards are known to work fine at 50 MHz. ALSO NOTE: this doesn't update the "sc7280-chrome-common.dtsi" file which is used by both herobrine boards and IDP. At the moment the IDP boards aren't configuring a drive strength of 8 and it seems safer to just leave them at the slower speed if they're already working. Signed-off-by: Douglas Anderson <dianders@chromium.org> --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 4 ++++ 1 file changed, 4 insertions(+)