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[v2,1/3] dt-bindings: riscv: document cbom-block-size

Message ID 20220511214132.2281431-2-heiko@sntech.de
State New
Headers show
Series [v2,1/3] dt-bindings: riscv: document cbom-block-size | expand

Commit Message

Heiko Stuebner May 11, 2022, 9:41 p.m. UTC
The Zicbom operates on a block-size defined for the cpu-core,
which does not necessarily match other cache-sizes used.

So add the necessary property for the system to know the core's
block-size.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++
 1 file changed, 7 insertions(+)
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..b179bfd155a3 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -63,6 +63,13 @@  properties:
       - riscv,sv48
       - riscv,none
 
+  riscv,cbom-block-size:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Blocksize in bytes for the Zicbom cache operations. The block
+      size is a property of the core itself and does not necessarily
+      match other software defined cache sizes.
+
   riscv,isa:
     description:
       Identifies the specific RISC-V instruction set architecture