[2/3] phy: qcom-qmp: Add USB3 5NM QMP UNI registers

Add all registers defines from qcom,usb3-5nm-qmp-uni.h of the msm-5.4
kernel. Offsets are adjusted to be relative to each sub-block, as we
describe the individual pieces in the upstream kernel and "5NM" are
injected in the defines to not collide with existing constants.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
 .../phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h  | 617 ++++++++++++++++++
 1 file changed, 617 insertions(+)
 create mode 100644 drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h

On 13-05-22, 15:53, Bjorn Andersson wrote:
> Add all registers defines from qcom,usb3-5nm-qmp-uni.h of the msm-5.4
> kernel. Offsets are adjusted to be relative to each sub-block, as we
> describe the individual pieces in the upstream kernel and "5NM" are
> injected in the defines to not collide with existing constants.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>  .../phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h  | 617 ++++++++++++++++++
>  1 file changed, 617 insertions(+)
>  create mode 100644 drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> new file mode 100644
> index 000000000000..b912e50825f9
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> @@ -0,0 +1,617 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.

should this be 2022 or add Linaro one for 2022..?

> + */
> +
> +#ifndef PHY_QCOM_USB3_5NM_QMP_UNI_H_
> +#define PHY_QCOM_USB3_5NM_QMP_UNI_H_
> +
> +/* Module: USB3_UNI_PHY_QSERDES_COM_QSERDES_COM_PCIE_USB3_UNI_QMP_PLL */
> +#define USB3_5NM_UNI_QSERDES_COM_ATB_SEL1			0x000
> +#define USB3_5NM_UNI_QSERDES_COM_ATB_SEL2			0x004
> +#define USB3_5NM_UNI_QSERDES_COM_FREQ_UPDATE			0x008
> +#define USB3_5NM_UNI_QSERDES_COM_BG_TIMER			0x00c
> +#define USB3_5NM_UNI_QSERDES_COM_SSC_EN_CENTER			0x010
> +#define USB3_5NM_UNI_QSERDES_COM_SSC_ADJ_PER1			0x014
> +#define USB3_5NM_UNI_QSERDES_COM_SSC_ADJ_PER2			0x018
> +#define USB3_5NM_UNI_QSERDES_COM_SSC_PER1			0x01c
> +#define USB3_5NM_UNI_QSERDES_COM_SSC_PER2			0x020
> +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0		0x024
> +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0		0x028
> +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE0		0x02c
> +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1		0x030
> +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1		0x034
> +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE1		0x038
> +#define USB3_5NM_UNI_QSERDES_COM_POST_DIV			0x03c
> +#define USB3_5NM_UNI_QSERDES_COM_POST_DIV_MUX			0x040
> +#define USB3_5NM_UNI_QSERDES_COM_BIAS_EN_CLKBUFLR_EN		0x044
> +#define USB3_5NM_UNI_QSERDES_COM_CLK_ENABLE1			0x048
> +#define USB3_5NM_UNI_QSERDES_COM_SYS_CLK_CTRL			0x04c
> +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE		0x050
> +#define USB3_5NM_UNI_QSERDES_COM_PLL_EN				0x054
> +#define USB3_5NM_UNI_QSERDES_COM_PLL_IVCO			0x058
> +#define USB3_5NM_UNI_QSERDES_COM_CMN_IETRIM			0x05c
> +#define USB3_5NM_UNI_QSERDES_COM_CMN_IPTRIM			0x060
> +#define USB3_5NM_UNI_QSERDES_COM_EP_CLOCK_DETECT_CTRL		0x064
> +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_DET_COMP_STATUS		0x068
> +#define USB3_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE0		0x06c
> +#define USB3_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE1		0x070
> +#define USB3_5NM_UNI_QSERDES_COM_CP_CTRL_MODE0			0x074
> +#define USB3_5NM_UNI_QSERDES_COM_CP_CTRL_MODE1			0x078
> +#define USB3_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE0		0x07c
> +#define USB3_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE1		0x080
> +#define USB3_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE0		0x084
> +#define USB3_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE1		0x088
> +#define USB3_5NM_UNI_QSERDES_COM_PLL_CNTRL			0x08c
> +#define USB3_5NM_UNI_QSERDES_COM_BIAS_EN_CTRL_BY_PSM		0x090
> +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_EN_SEL			0x094
> +#define USB3_5NM_UNI_QSERDES_COM_CML_SYSCLK_SEL			0x098
> +#define USB3_5NM_UNI_QSERDES_COM_RESETSM_CNTRL			0x09c
> +#define USB3_5NM_UNI_QSERDES_COM_RESETSM_CNTRL2			0x0a0
> +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP_EN			0x0a4
> +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP_CFG			0x0a8
> +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE0		0x0ac
> +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE0		0x0b0
> +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE1		0x0b4
> +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE1		0x0b8
> +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MODE0		0x0bc
> +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE0		0x0c0
> +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MODE1		0x0c4
> +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE1		0x0c8
> +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0		0x0cc
> +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0		0x0d0
> +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0		0x0d4
> +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1		0x0d8
> +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1		0x0dc
> +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1		0x0e0
> +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_INITVAL		0x0e4
> +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_EN			0x0e8
> +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE0		0x0ec
> +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE0		0x0f0
> +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE1		0x0f4
> +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE1		0x0f8
> +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0		0x0fc
> +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1		0x100
> +#define USB3_5NM_UNI_QSERDES_COM_VCOCAL_DEADMAN_CTRL		0x104
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_CTRL			0x108
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAP			0x10c
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE0		0x110
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE0		0x114
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE1		0x118
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE1		0x11c
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL1		0x120
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL2		0x124
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL1		0x128
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL2		0x12c
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL1		0x130
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL2		0x134
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER1		0x138
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER2		0x13c
> +#define USB3_5NM_UNI_QSERDES_COM_CMN_STATUS			0x140
> +#define USB3_5NM_UNI_QSERDES_COM_RESET_SM_STATUS		0x144
> +#define USB3_5NM_UNI_QSERDES_COM_RESTRIM_CODE_STATUS		0x148
> +#define USB3_5NM_UNI_QSERDES_COM_PLLCAL_CODE1_STATUS		0x14c
> +#define USB3_5NM_UNI_QSERDES_COM_PLLCAL_CODE2_STATUS		0x150
> +#define USB3_5NM_UNI_QSERDES_COM_CLK_SELECT			0x154
> +#define USB3_5NM_UNI_QSERDES_COM_HSCLK_SEL			0x158
> +#define USB3_5NM_UNI_QSERDES_COM_HSCLK_HS_SWITCH_SEL		0x15c
> +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_BINCODE_STATUS	0x160
> +#define USB3_5NM_UNI_QSERDES_COM_PLL_ANALOG			0x164
> +#define USB3_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE0		0x168
> +#define USB3_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE1		0x16c
> +#define USB3_5NM_UNI_QSERDES_COM_SW_RESET			0x170
> +#define USB3_5NM_UNI_QSERDES_COM_CORE_CLK_EN			0x174
> +#define USB3_5NM_UNI_QSERDES_COM_C_READY_STATUS			0x178
> +#define USB3_5NM_UNI_QSERDES_COM_CMN_CONFIG			0x17c
> +#define USB3_5NM_UNI_QSERDES_COM_CMN_RATE_OVERRIDE		0x180
> +#define USB3_5NM_UNI_QSERDES_COM_SVS_MODE_CLK_SEL		0x184
> +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS0			0x188
> +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS1			0x18c
> +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS2			0x190
> +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS3			0x194
> +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS_SEL			0x198
> +#define USB3_5NM_UNI_QSERDES_COM_CMN_MISC1			0x19c
> +#define USB3_5NM_UNI_QSERDES_COM_CMN_MODE			0x1a0
> +#define USB3_5NM_UNI_QSERDES_COM_CMN_MODE_CONTD			0x1a4
> +#define USB3_5NM_UNI_QSERDES_COM_VCO_DC_LEVEL_CTRL		0x1a8
> +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0x1ac
> +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1b0
> +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0x1b4
> +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1b8
> +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL		0x1bc
> +#define USB3_5NM_UNI_QSERDES_COM_RESERVED_1			0x1c0
> +#define USB3_5NM_UNI_QSERDES_COM_MODE_OPERATION_STATUS		0x1c4
> +
> +/* Module: USB3_UNI_PHY_QSERDES_TX_PCIE_USB3_UNI_QMP_TX */
> +#define USB3_5NM_UNI_QSERDES_TX_BIST_MODE_LANENO		0x000
> +#define USB3_5NM_UNI_QSERDES_TX_BIST_INVERT			0x004
> +#define USB3_5NM_UNI_QSERDES_TX_CLKBUF_ENABLE			0x008
> +#define USB3_5NM_UNI_QSERDES_TX_TX_EMP_POST1_LVL		0x00c
> +#define USB3_5NM_UNI_QSERDES_TX_TX_IDLE_LVL_LARGE_AMP		0x010
> +#define USB3_5NM_UNI_QSERDES_TX_TX_DRV_LVL			0x014
> +#define USB3_5NM_UNI_QSERDES_TX_TX_DRV_LVL_OFFSET		0x018
> +#define USB3_5NM_UNI_QSERDES_TX_RESET_TSYNC_EN			0x01c
> +#define USB3_5NM_UNI_QSERDES_TX_PRE_STALL_LDO_BOOST_EN		0x020
> +#define USB3_5NM_UNI_QSERDES_TX_TX_BAND				0x024
> +#define USB3_5NM_UNI_QSERDES_TX_SLEW_CNTL			0x028
> +#define USB3_5NM_UNI_QSERDES_TX_INTERFACE_SELECT		0x02c
> +#define USB3_5NM_UNI_QSERDES_TX_LPB_EN				0x030
> +#define USB3_5NM_UNI_QSERDES_TX_RES_CODE_LANE_TX		0x034
> +#define USB3_5NM_UNI_QSERDES_TX_RES_CODE_LANE_RX		0x038
> +#define USB3_5NM_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX		0x03c
> +#define USB3_5NM_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX		0x040
> +#define USB3_5NM_UNI_QSERDES_TX_PERL_LENGTH1			0x044
> +#define USB3_5NM_UNI_QSERDES_TX_PERL_LENGTH2			0x048
> +#define USB3_5NM_UNI_QSERDES_TX_SERDES_BYP_EN_OUT		0x04c
> +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS_SEL			0x050
> +#define USB3_5NM_UNI_QSERDES_TX_TRANSCEIVER_BIAS_EN		0x054
> +#define USB3_5NM_UNI_QSERDES_TX_HIGHZ_DRVR_EN			0x058
> +#define USB3_5NM_UNI_QSERDES_TX_TX_POL_INV			0x05c
> +#define USB3_5NM_UNI_QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN	0x060
> +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN1			0x064
> +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN2			0x068
> +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN3			0x06c
> +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN4			0x070
> +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN5			0x074
> +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN6			0x078
> +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN7			0x07c
> +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN8			0x080
> +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_1			0x084
> +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_2			0x088
> +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_3			0x08c
> +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_4			0x090
> +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_5			0x094
> +#define USB3_5NM_UNI_QSERDES_TX_ATB_SEL1			0x098
> +#define USB3_5NM_UNI_QSERDES_TX_ATB_SEL2			0x09c
> +#define USB3_5NM_UNI_QSERDES_TX_RCV_DETECT_LVL			0x0a0
> +#define USB3_5NM_UNI_QSERDES_TX_RCV_DETECT_LVL_2		0x0a4
> +#define USB3_5NM_UNI_QSERDES_TX_PRBS_SEED1			0x0a8
> +#define USB3_5NM_UNI_QSERDES_TX_PRBS_SEED2			0x0ac
> +#define USB3_5NM_UNI_QSERDES_TX_PRBS_SEED3			0x0b0
> +#define USB3_5NM_UNI_QSERDES_TX_PRBS_SEED4			0x0b4
> +#define USB3_5NM_UNI_QSERDES_TX_RESET_GEN			0x0b8
> +#define USB3_5NM_UNI_QSERDES_TX_RESET_GEN_MUXES			0x0bc
> +#define USB3_5NM_UNI_QSERDES_TX_TRAN_DRVR_EMP_EN		0x0c0
> +#define USB3_5NM_UNI_QSERDES_TX_TX_INTERFACE_MODE		0x0c4
> +#define USB3_5NM_UNI_QSERDES_TX_VMODE_CTRL1			0x0c8
> +#define USB3_5NM_UNI_QSERDES_TX_ALOG_OBSV_BUS_CTRL_1		0x0cc
> +#define USB3_5NM_UNI_QSERDES_TX_BIST_STATUS			0x0d0
> +#define USB3_5NM_UNI_QSERDES_TX_BIST_ERROR_COUNT1		0x0d4
> +#define USB3_5NM_UNI_QSERDES_TX_BIST_ERROR_COUNT2		0x0d8
> +#define USB3_5NM_UNI_QSERDES_TX_ALOG_OBSV_BUS_STATUS_1		0x0dc
> +#define USB3_5NM_UNI_QSERDES_TX_LANE_DIG_CONFIG			0x0e0
> +#define USB3_5NM_UNI_QSERDES_TX_PI_QEC_CTRL			0x0e4
> +#define USB3_5NM_UNI_QSERDES_TX_PRE_EMPH			0x0e8
> +#define USB3_5NM_UNI_QSERDES_TX_SW_RESET			0x0ec
> +#define USB3_5NM_UNI_QSERDES_TX_DCC_OFFSET			0x0f0
> +#define USB3_5NM_UNI_QSERDES_TX_DCC_CMUX_POSTCAL_OFFSET		0x0f4
> +#define USB3_5NM_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL1		0x0f8
> +#define USB3_5NM_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL2		0x0fc
> +#define USB3_5NM_UNI_QSERDES_TX_DIG_BKUP_CTRL			0x100
> +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS0			0x104
> +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS1			0x108
> +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS2			0x10c
> +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS3			0x110
> +#define USB3_5NM_UNI_QSERDES_TX_READ_EQCODE			0x114
> +#define USB3_5NM_UNI_QSERDES_TX_READ_OFFSETCODE			0x118
> +#define USB3_5NM_UNI_QSERDES_TX_IA_ERROR_COUNTER_LOW		0x11c
> +#define USB3_5NM_UNI_QSERDES_TX_IA_ERROR_COUNTER_HIGH		0x120
> +#define USB3_5NM_UNI_QSERDES_TX_VGA_READ_CODE			0x124
> +#define USB3_5NM_UNI_QSERDES_TX_VTH_READ_CODE			0x128
> +#define USB3_5NM_UNI_QSERDES_TX_DFE_TAP1_READ_CODE		0x12c
> +#define USB3_5NM_UNI_QSERDES_TX_DFE_TAP2_READ_CODE		0x130
> +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_I			0x134
> +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_IBAR		0x138
> +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_Q			0x13c
> +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_QBAR		0x140
> +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_A			0x144
> +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_ABAR		0x148
> +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_SM_ON		0x14c
> +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_CAL_DONE		0x150
> +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_SIGNERROR		0x154
> +#define USB3_5NM_UNI_QSERDES_TX_DCC_CAL_STATUS			0x158
> +#define USB3_5NM_UNI_QSERDES_TX_DCC_READ_CODE_STATUS		0x15c
> +
> +/* Module: USB3_UNI_PHY_QSERDES_RX_QSERDES_RX_PCIE_USB3_UNI_QMP_RX */
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN_HALF		0x000
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN_QUARTER		0x004
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN			0x008
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN_HALF		0x00c
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN_QUARTER		0x010
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN			0x014
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_HALF		0x018
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER	0x01c
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN		0x020
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_HALF		0x024
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER	0x028
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN		0x02c
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN		0x030
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FO_TO_SO_DELAY		0x038
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH	0x040
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_PI_CONTROLS		0x044
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_PI_CTRL2			0x048
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SB2_THRESH1		0x04c
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SB2_THRESH2		0x050
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SB2_GAIN1			0x054
> +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SB2_GAIN2			0x058
> +#define USB3_5NM_UNI_QSERDES_RX_AUX_CONTROL			0x05c
> +#define USB3_5NM_UNI_QSERDES_RX_AUX_DATA_TCOARSE_TFINE		0x060
> +#define USB3_5NM_UNI_QSERDES_RX_RCLK_AUXDATA_SEL		0x064
> +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_ENABLE			0x068
> +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_INITP			0x06c
> +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_INITN			0x070
> +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_LVL			0x074
> +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_MODE			0x078
> +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_RESET			0x07c
> +#define USB3_5NM_UNI_QSERDES_RX_RX_TERM_BW			0x080
> +#define USB3_5NM_UNI_QSERDES_RX_RX_RCVR_IQ_EN			0x084
> +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_I_DC_OFFSETS		0x088
> +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS		0x08c
> +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_Q_DC_OFFSETS		0x090
> +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS		0x094
> +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_A_DC_OFFSETS		0x098
> +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS		0x09c
> +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_EN			0x0a0
> +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_ENABLES			0x0a4
> +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_SIGN			0x0a8
> +#define USB3_5NM_UNI_QSERDES_RX_RX_HIGHZ_HIGHRATE		0x0ac
> +#define USB3_5NM_UNI_QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET	0x0b0
> +#define USB3_5NM_UNI_QSERDES_RX_DFE_1				0x0b4
> +#define USB3_5NM_UNI_QSERDES_RX_DFE_2				0x0b8
> +#define USB3_5NM_UNI_QSERDES_RX_DFE_3				0x0bc
> +#define USB3_5NM_UNI_QSERDES_RX_DFE_4				0x0c0
> +#define USB3_5NM_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH1		0x0c4
> +#define USB3_5NM_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH2		0x0c8
> +#define USB3_5NM_UNI_QSERDES_RX_TX_ADAPT_POST_THRESH		0x0cc
> +#define USB3_5NM_UNI_QSERDES_RX_TX_ADAPT_MAIN_THRESH		0x0d0
> +#define USB3_5NM_UNI_QSERDES_RX_VGA_CAL_CNTRL1			0x0d4
> +#define USB3_5NM_UNI_QSERDES_RX_VGA_CAL_CNTRL2			0x0d8
> +#define USB3_5NM_UNI_QSERDES_RX_GM_CAL				0x0dc
> +#define USB3_5NM_UNI_QSERDES_RX_RX_VGA_GAIN2_LSB		0x0e0
> +#define USB3_5NM_UNI_QSERDES_RX_RX_VGA_GAIN2_MSB		0x0e4
> +#define USB3_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1		0x0e8
> +#define USB3_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2		0x0ec
> +#define USB3_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3		0x0f0
> +#define USB3_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4		0x0f4
> +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW		0x0f8
> +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH		0x0fc
> +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_MEASURE_TIME		0x100
> +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_ACCUMULATOR		0x104
> +#define USB3_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_LSB		0x108
> +#define USB3_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_MSB		0x10c
> +#define USB3_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x110
> +#define USB3_5NM_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2	0x114
> +#define USB3_5NM_UNI_QSERDES_RX_SIGDET_ENABLES			0x118
> +#define USB3_5NM_UNI_QSERDES_RX_SIGDET_CNTRL			0x11c
> +#define USB3_5NM_UNI_QSERDES_RX_SIGDET_LVL			0x120
> +#define USB3_5NM_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL		0x124
> +#define USB3_5NM_UNI_QSERDES_RX_RX_BAND				0x128
> +#define USB3_5NM_UNI_QSERDES_RX_CDR_FREEZE_UP_DN		0x12c
> +#define USB3_5NM_UNI_QSERDES_RX_CDR_RESET_OVERRIDE		0x130
> +#define USB3_5NM_UNI_QSERDES_RX_RX_INTERFACE_MODE		0x134
> +#define USB3_5NM_UNI_QSERDES_RX_JITTER_GEN_MODE			0x138
> +#define USB3_5NM_UNI_QSERDES_RX_SJ_AMP1				0x13c
> +#define USB3_5NM_UNI_QSERDES_RX_SJ_AMP2				0x140
> +#define USB3_5NM_UNI_QSERDES_RX_SJ_PER1				0x144
> +#define USB3_5NM_UNI_QSERDES_RX_SJ_PER2				0x148
> +#define USB3_5NM_UNI_QSERDES_RX_PPM_OFFSET1			0x14c
> +#define USB3_5NM_UNI_QSERDES_RX_PPM_OFFSET2			0x150
> +#define USB3_5NM_UNI_QSERDES_RX_SIGN_PPM_PERIOD1		0x154
> +#define USB3_5NM_UNI_QSERDES_RX_SIGN_PPM_PERIOD2		0x158
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_LOW			0x15c
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH			0x160
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH2		0x164
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH3		0x168
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH4		0x16c
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_LOW			0x170
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH			0x174
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH2		0x178
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH3		0x17c
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH4		0x180
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_LOW			0x184
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH			0x188
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH2		0x18c
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH3		0x190
> +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH4		0x194
> +#define USB3_5NM_UNI_QSERDES_RX_PHPRE_CTRL			0x198
> +#define USB3_5NM_UNI_QSERDES_RX_PHPRE_INITVAL			0x19c
> +#define USB3_5NM_UNI_QSERDES_RX_DFE_EN_TIMER			0x1a0
> +#define USB3_5NM_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET	0x1a4
> +#define USB3_5NM_UNI_QSERDES_RX_DCC_CTRL1			0x1a8
> +#define USB3_5NM_UNI_QSERDES_RX_DCC_CTRL2			0x1ac
> +#define USB3_5NM_UNI_QSERDES_RX_VTH_CODE			0x1b0
> +#define USB3_5NM_UNI_QSERDES_RX_VTH_MIN_THRESH			0x1b4
> +#define USB3_5NM_UNI_QSERDES_RX_VTH_MAX_THRESH			0x1b8
> +#define USB3_5NM_UNI_QSERDES_RX_ALOG_OBSV_BUS_CTRL_1		0x1bc
> +#define USB3_5NM_UNI_QSERDES_RX_PI_CTRL1			0x1c0
> +#define USB3_5NM_UNI_QSERDES_RX_PI_CTRL2			0x1c4
> +#define USB3_5NM_UNI_QSERDES_RX_PI_QUAD				0x1c8
> +#define USB3_5NM_UNI_QSERDES_RX_IDATA1				0x1cc
> +#define USB3_5NM_UNI_QSERDES_RX_IDATA2				0x1d0
> +#define USB3_5NM_UNI_QSERDES_RX_AUX_DATA1			0x1d4
> +#define USB3_5NM_UNI_QSERDES_RX_AUX_DATA2			0x1d8
> +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_OUTP			0x1dc
> +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_OUTN			0x1e0
> +#define USB3_5NM_UNI_QSERDES_RX_RX_SIGDET			0x1e4
> +#define USB3_5NM_UNI_QSERDES_RX_ALOG_OBSV_BUS_STATUS_1		0x1e8
> +
> +/* Module:  USB3_UNI_PCS_LN_PCIE_USB3_UNI_PCS_LANE */
> +#define USB3_5NM_UNI_PCS_LN_PCS_STATUS1				0x00
> +#define USB3_5NM_UNI_PCS_LN_PCS_STATUS2				0x04
> +#define USB3_5NM_UNI_PCS_LN_PCS_STATUS2_CLEAR			0x08
> +#define USB3_5NM_UNI_PCS_LN_PCS_STATUS3				0x0c
> +#define USB3_5NM_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS		0x10
> +#define USB3_5NM_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS		0x14
> +#define USB3_5NM_UNI_PCS_LN_BIST_CHK_STATUS			0x18
> +#define USB3_5NM_UNI_PCS_LN_INSIG_SW_CTRL1			0x1c
> +#define USB3_5NM_UNI_PCS_LN_INSIG_MX_CTRL1			0x20
> +#define USB3_5NM_UNI_PCS_LN_OUTSIG_SW_CTRL1			0x24
> +#define USB3_5NM_UNI_PCS_LN_OUTSIG_MX_CTRL1			0x28
> +#define USB3_5NM_UNI_PCS_LN_TEST_CONTROL1			0x2c
> +#define USB3_5NM_UNI_PCS_LN_BIST_CTRL				0x30
> +#define USB3_5NM_UNI_PCS_LN_PRBS_SEED0				0x34
> +#define USB3_5NM_UNI_PCS_LN_PRBS_SEED1				0x38
> +#define USB3_5NM_UNI_PCS_LN_FIXED_PAT_CTRL			0x3c
> +#define USB3_5NM_UNI_PCS_LN_EQ_CONFIG				0x40
> +#define USB3_5NM_UNI_PCS_LN_TEST_CONTROL2			0x44
> +#define USB3_5NM_UNI_PCS_LN_TEST_CONTROL3			0x48
> +
> +/* Module: USB3_UNI_PCS_PCIE_LN_PCIE_USB3_UNI_PCS_PCIE_LANE */
> +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST	0x00
> +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST_RS	0x04
> +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_EN		0x08
> +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_DSBL_L			0x0c
> +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_DSBL_H			0x10
> +#define USB3_5NM_UNI_PCS_PCIE_LN_LANE_OFF_CONFIG		0x14
> +#define USB3_5NM_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG1		0x18
> +#define USB3_5NM_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG2		0x1c
> +#define USB3_5NM_UNI_PCS_PCIE_LN_PCIE_PCS_STATUS		0x20
> +#define USB3_5NM_UNI_PCS_PCIE_LN_INSIG_SW_CTRL2			0x24
> +#define USB3_5NM_UNI_PCS_PCIE_LN_INSIG_MX_CTRL2			0x28
> +
> +/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS */
> +#define USB3_5NM_UNI_PCS_SW_RESET				0x000
> +#define USB3_5NM_UNI_PCS_REVISION_ID0				0x004
> +#define USB3_5NM_UNI_PCS_REVISION_ID1				0x008
> +#define USB3_5NM_UNI_PCS_REVISION_ID2				0x00c
> +#define USB3_5NM_UNI_PCS_REVISION_ID3				0x010
> +#define USB3_5NM_UNI_PCS_PCS_STATUS1				0x014
> +#define USB3_5NM_UNI_PCS_PCS_STATUS2				0x018
> +#define USB3_5NM_UNI_PCS_PCS_STATUS3				0x01c
> +#define USB3_5NM_UNI_PCS_PCS_STATUS4				0x020
> +#define USB3_5NM_UNI_PCS_PCS_STATUS5				0x024
> +#define USB3_5NM_UNI_PCS_PCS_STATUS6				0x028
> +#define USB3_5NM_UNI_PCS_PCS_STATUS7				0x02c
> +#define USB3_5NM_UNI_PCS_DEBUG_BUS_0_STATUS			0x030
> +#define USB3_5NM_UNI_PCS_DEBUG_BUS_1_STATUS			0x034
> +#define USB3_5NM_UNI_PCS_DEBUG_BUS_2_STATUS			0x038
> +#define USB3_5NM_UNI_PCS_DEBUG_BUS_3_STATUS			0x03c
> +#define USB3_5NM_UNI_PCS_POWER_DOWN_CONTROL			0x040
> +#define USB3_5NM_UNI_PCS_START_CONTROL				0x044
> +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL1				0x048
> +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL2				0x04c
> +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL3				0x050
> +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL4				0x054
> +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL5				0x058
> +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL6				0x05c
> +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL7				0x060
> +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL8				0x064
> +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL1				0x068
> +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL2				0x06c
> +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL3				0x070
> +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL4				0x074
> +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL5				0x078
> +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL7				0x07c
> +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL8				0x080
> +#define USB3_5NM_UNI_PCS_OUTSIG_SW_CTRL1			0x084
> +#define USB3_5NM_UNI_PCS_OUTSIG_MX_CTRL1			0x088
> +#define USB3_5NM_UNI_PCS_CLAMP_ENABLE				0x08c
> +#define USB3_5NM_UNI_PCS_POWER_STATE_CONFIG1			0x090
> +#define USB3_5NM_UNI_PCS_POWER_STATE_CONFIG2			0x094
> +#define USB3_5NM_UNI_PCS_FLL_CNTRL1				0x098
> +#define USB3_5NM_UNI_PCS_FLL_CNTRL2				0x09c
> +#define USB3_5NM_UNI_PCS_FLL_CNT_VAL_L				0x0a0
> +#define USB3_5NM_UNI_PCS_FLL_CNT_VAL_H_TOL			0x0a4
> +#define USB3_5NM_UNI_PCS_FLL_MAN_CODE				0x0a8
> +#define USB3_5NM_UNI_PCS_TEST_CONTROL1				0x0ac
> +#define USB3_5NM_UNI_PCS_TEST_CONTROL2				0x0b0
> +#define USB3_5NM_UNI_PCS_TEST_CONTROL3				0x0b4
> +#define USB3_5NM_UNI_PCS_TEST_CONTROL4				0x0b8
> +#define USB3_5NM_UNI_PCS_TEST_CONTROL5				0x0bc
> +#define USB3_5NM_UNI_PCS_TEST_CONTROL6				0x0c0
> +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG1			0x0c4
> +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG2			0x0c8
> +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG3			0x0cc
> +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG4			0x0d0
> +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG5			0x0d4
> +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG6			0x0d8
> +#define USB3_5NM_UNI_PCS_REFGEN_REQ_CONFIG1			0x0dc
> +#define USB3_5NM_UNI_PCS_REFGEN_REQ_CONFIG2			0x0e0
> +#define USB3_5NM_UNI_PCS_REFGEN_REQ_CONFIG3			0x0e4
> +#define USB3_5NM_UNI_PCS_BIST_CTRL				0x0e8
> +#define USB3_5NM_UNI_PCS_PRBS_POLY0				0x0ec
> +#define USB3_5NM_UNI_PCS_PRBS_POLY1				0x0f0
> +#define USB3_5NM_UNI_PCS_FIXED_PAT0				0x0f4
> +#define USB3_5NM_UNI_PCS_FIXED_PAT1				0x0f8
> +#define USB3_5NM_UNI_PCS_FIXED_PAT2				0x0fc
> +#define USB3_5NM_UNI_PCS_FIXED_PAT3				0x100
> +#define USB3_5NM_UNI_PCS_FIXED_PAT4				0x104
> +#define USB3_5NM_UNI_PCS_FIXED_PAT5				0x108
> +#define USB3_5NM_UNI_PCS_FIXED_PAT6				0x10c
> +#define USB3_5NM_UNI_PCS_FIXED_PAT7				0x110
> +#define USB3_5NM_UNI_PCS_FIXED_PAT8				0x114
> +#define USB3_5NM_UNI_PCS_FIXED_PAT9				0x118
> +#define USB3_5NM_UNI_PCS_FIXED_PAT10				0x11c
> +#define USB3_5NM_UNI_PCS_FIXED_PAT11				0x120
> +#define USB3_5NM_UNI_PCS_FIXED_PAT12				0x124
> +#define USB3_5NM_UNI_PCS_FIXED_PAT13				0x128
> +#define USB3_5NM_UNI_PCS_FIXED_PAT14				0x12c
> +#define USB3_5NM_UNI_PCS_FIXED_PAT15				0x130
> +#define USB3_5NM_UNI_PCS_TXMGN_CONFIG				0x134
> +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V0				0x138
> +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V1				0x13c
> +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V2				0x140
> +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V3				0x144
> +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V4				0x148
> +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V0_RS			0x14c
> +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V1_RS			0x150
> +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V2_RS			0x154
> +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V3_RS			0x158
> +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V4_RS			0x15c
> +#define USB3_5NM_UNI_PCS_G3S2_TXMGN_MAIN			0x160
> +#define USB3_5NM_UNI_PCS_G3S2_TXMGN_MAIN_RS			0x164
> +#define USB3_5NM_UNI_PCS_G12S1_TXDEEMPH_M6DB			0x168
> +#define USB3_5NM_UNI_PCS_G12S1_TXDEEMPH_M3P5DB			0x16c
> +#define USB3_5NM_UNI_PCS_G3S2_PRE_GAIN				0x170
> +#define USB3_5NM_UNI_PCS_G3S2_POST_GAIN				0x174
> +#define USB3_5NM_UNI_PCS_G3S2_PRE_POST_OFFSET			0x178
> +#define USB3_5NM_UNI_PCS_G3S2_PRE_GAIN_RS			0x17c
> +#define USB3_5NM_UNI_PCS_G3S2_POST_GAIN_RS			0x180
> +#define USB3_5NM_UNI_PCS_G3S2_PRE_POST_OFFSET_RS		0x184
> +#define USB3_5NM_UNI_PCS_RX_SIGDET_LVL				0x188
> +#define USB3_5NM_UNI_PCS_RX_SIGDET_DTCT_CNTRL			0x18c
> +#define USB3_5NM_UNI_PCS_RCVR_DTCT_DLY_P1U2_L			0x190
> +#define USB3_5NM_UNI_PCS_RCVR_DTCT_DLY_P1U2_H			0x194
> +#define USB3_5NM_UNI_PCS_RATE_SLEW_CNTRL1			0x198
> +#define USB3_5NM_UNI_PCS_RATE_SLEW_CNTRL2			0x19c
> +#define USB3_5NM_UNI_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x1a0
> +#define USB3_5NM_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L		0x1a4
> +#define USB3_5NM_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H		0x1a8
> +#define USB3_5NM_UNI_PCS_TSYNC_RSYNC_TIME			0x1ac
> +#define USB3_5NM_UNI_PCS_CDR_RESET_TIME				0x1b0
> +#define USB3_5NM_UNI_PCS_TSYNC_DLY_TIME				0x1b4
> +#define USB3_5NM_UNI_PCS_ELECIDLE_DLY_SEL			0x1b8
> +#define USB3_5NM_UNI_PCS_CMN_ACK_OUT_SEL			0x1bc
> +#define USB3_5NM_UNI_PCS_ALIGN_DETECT_CONFIG1			0x1c0
> +#define USB3_5NM_UNI_PCS_ALIGN_DETECT_CONFIG2			0x1c4
> +#define USB3_5NM_UNI_PCS_ALIGN_DETECT_CONFIG3			0x1c8
> +#define USB3_5NM_UNI_PCS_ALIGN_DETECT_CONFIG4			0x1cc
> +#define USB3_5NM_UNI_PCS_PCS_TX_RX_CONFIG			0x1d0
> +#define USB3_5NM_UNI_PCS_RX_IDLE_DTCT_CNTRL			0x1d4
> +#define USB3_5NM_UNI_PCS_RX_DCC_CAL_CONFIG			0x1d8
> +#define USB3_5NM_UNI_PCS_EQ_CONFIG1				0x1dc
> +#define USB3_5NM_UNI_PCS_EQ_CONFIG2				0x1e0
> +#define USB3_5NM_UNI_PCS_EQ_CONFIG3				0x1e4
> +#define USB3_5NM_UNI_PCS_EQ_CONFIG4				0x1e8
> +#define USB3_5NM_UNI_PCS_EQ_CONFIG5				0x1ec
> +
> +/* Module: USB3_UNI_PHY_PCIE_PCS */
> +#define USB3_5NM_UNI_PCS_PCIE_INT_AUX_CLK_STATUS		0x00
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_STATUS			0x04
> +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG1		0x08
> +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG2		0x0c
> +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG3		0x10
> +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG4		0x14
> +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG5		0x18
> +#define USB3_5NM_UNI_PCS_PCIE_PCS_TX_RX_CONFIG			0x1c
> +#define USB3_5NM_UNI_PCS_PCIE_ENDPOINT_REFCLK_DRIVE		0x20
> +#define USB3_5NM_UNI_PCS_PCIE_ENDPOINT_REFCLK_CNTRL		0x24
> +#define USB3_5NM_UNI_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK	0x28
> +#define USB3_5NM_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L		0x2c
> +#define USB3_5NM_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H		0x30
> +#define USB3_5NM_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL1		0x34
> +#define USB3_5NM_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL2		0x38
> +#define USB3_5NM_UNI_PCS_PCIE_SIGDET_CNTRL			0x3c
> +#define USB3_5NM_UNI_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME		0x40
> +#define USB3_5NM_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L	0x44
> +#define USB3_5NM_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H	0x48
> +#define USB3_5NM_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L	0x4c
> +#define USB3_5NM_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H	0x50
> +#define USB3_5NM_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG1		0x54
> +#define USB3_5NM_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG2		0x58
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG1			0x5c
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG2			0x60
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG3			0x64
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG4			0x68
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG5			0x6c
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG6			0x70
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG7			0x74
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1		0x78
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2		0x7c
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3		0x80
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4		0x84
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5		0x88
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6		0x8c
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7		0x90
> +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_ACTIONS			0x94
> +#define USB3_5NM_UNI_PCS_PCIE_LOCAL_FS				0x98
> +#define USB3_5NM_UNI_PCS_PCIE_LOCAL_LF				0x9c
> +#define USB3_5NM_UNI_PCS_PCIE_LOCAL_FS_RS			0xa0
> +#define USB3_5NM_UNI_PCS_PCIE_EQ_CONFIG1			0xa4
> +#define USB3_5NM_UNI_PCS_PCIE_EQ_CONFIG2			0xa8
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P0_P1_PRE			0xac
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P2_P3_PRE			0xb0
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P4_P5_PRE			0xb4
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P6_P7_PRE			0xb8
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P8_P9_PRE			0xbc
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P10_PRE			0xc0
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P1_P3_PRE_RS		0xc4
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P4_P5_PRE_RS		0xc8
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P6_P9_PRE_RS		0xcc
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P0_P1_POST			0xd0
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P2_P3_POST			0xd4
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P4_P5_POST			0xd8
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P6_P7_POST			0xdc
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P8_P9_POST			0xe0
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P10_POST			0xe4
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P1_P3_POST_RS		0xe8
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P4_P5_POST_RS		0xec
> +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P6_P9_POST_RS		0xf0
> +#define USB3_5NM_UNI_PCS_PCIE_RXEQEVAL_TIME			0xf4
> +
> +/* Module: USB3_UNI_PHY_PCIE_PCS_DEBUG_INTGEN */
> +#define USB3_5NM_UNI_PCS_INTGEN_INTGEN_STATUS1			0x00
> +#define USB3_5NM_UNI_PCS_INTGEN_INTGEN_STATUS2			0x04
> +#define USB3_5NM_UNI_PCS_INTGEN_CONFIG1				0x08
> +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG1		0x0c
> +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG2		0x10
> +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG3		0x14
> +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG4		0x18
> +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG5		0x1c
> +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG1		0x20
> +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG2		0x24
> +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG3		0x28
> +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG4		0x2c
> +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG5		0x30
> +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG1		0x34
> +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG2		0x38
> +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG3		0x3c
> +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG4		0x40
> +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG5		0x44
> +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG1		0x48
> +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG2		0x4c
> +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG3		0x50
> +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG4		0x54
> +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG5		0x58
> +
> +
> +/* Module: USB3_UNI_PCS_USB3_PCIE_USB3_UNI_PCS_USB3 */
> +#define USB3_5NM_UNI_PCS_USB3_POWER_STATE_CONFIG1		0x00
> +#define USB3_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS		0x04
> +#define USB3_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL		0x08
> +#define USB3_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL2		0x0c
> +#define USB3_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS	0x10
> +#define USB3_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR		0x14
> +#define USB3_5NM_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL		0x18
> +#define USB3_5NM_UNI_PCS_USB3_LFPS_TX_ECSTART			0x1c
> +#define USB3_5NM_UNI_PCS_USB3_LFPS_PER_TIMER_VAL		0x20
> +#define USB3_5NM_UNI_PCS_USB3_LFPS_TX_END_CNT_U3_START		0x24
> +#define USB3_5NM_UNI_PCS_USB3_LFPS_CONFIG1			0x28
> +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_LOCK_TIME		0x2c
> +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME		0x30
> +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_CTLE_TIME		0x34
> +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2		0x38
> +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2		0x3c
> +#define USB3_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L		0x40
> +#define USB3_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H		0x44
> +#define USB3_5NM_UNI_PCS_USB3_ARCVR_DTCT_EN_PERIOD		0x48
> +#define USB3_5NM_UNI_PCS_USB3_ARCVR_DTCT_CM_DLY			0x4c
> +#define USB3_5NM_UNI_PCS_USB3_TXONESZEROS_RUN_LENGTH		0x50
> +#define USB3_5NM_UNI_PCS_USB3_ALFPS_DEGLITCH_VAL		0x54
> +#define USB3_5NM_UNI_PCS_USB3_SIGDET_STARTUP_TIMER_VAL		0x58
> +#define USB3_5NM_UNI_PCS_USB3_TEST_CONTROL			0x5c
> +#define USB3_5NM_UNI_PCS_USB3_RXTERMINATION_DLY_SEL		0x60
> +
> +#endif
> -- 
> 2.35.1

On 17-05-22, 16:01, Vinod Koul wrote:
> On 13-05-22, 15:53, Bjorn Andersson wrote:
> > Add all registers defines from qcom,usb3-5nm-qmp-uni.h of the msm-5.4
> > kernel. Offsets are adjusted to be relative to each sub-block, as we
> > describe the individual pieces in the upstream kernel and "5NM" are
> > injected in the defines to not collide with existing constants.
> > 
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> >  .../phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h  | 617 ++++++++++++++++++
> >  1 file changed, 617 insertions(+)
> >  create mode 100644 drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> > 
> > diff --git a/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> > new file mode 100644
> > index 000000000000..b912e50825f9
> > --- /dev/null
> > +++ b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> > @@ -0,0 +1,617 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> 
> should this be 2022 or add Linaro one for 2022..?
> 
> > + */
> > +
> > +#ifndef PHY_QCOM_USB3_5NM_QMP_UNI_H_
> > +#define PHY_QCOM_USB3_5NM_QMP_UNI_H_
> > +
> > +/* Module: USB3_UNI_PHY_QSERDES_COM_QSERDES_COM_PCIE_USB3_UNI_QMP_PLL */
> > +#define USB3_5NM_UNI_QSERDES_COM_ATB_SEL1			0x000
> > +#define USB3_5NM_UNI_QSERDES_COM_ATB_SEL2			0x004
> > +#define USB3_5NM_UNI_QSERDES_COM_FREQ_UPDATE			0x008
> > +#define USB3_5NM_UNI_QSERDES_COM_BG_TIMER			0x00c
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_EN_CENTER			0x010
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_ADJ_PER1			0x014
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_ADJ_PER2			0x018
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_PER1			0x01c
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_PER2			0x020
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0		0x024
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0		0x028

this seems to be QSERDES_V3_COM_* uptill now...

> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE0		0x02c
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1		0x030
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1		0x034
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE1		0x038
> > +#define USB3_5NM_UNI_QSERDES_COM_POST_DIV			0x03c
> > +#define USB3_5NM_UNI_QSERDES_COM_POST_DIV_MUX			0x040
> > +#define USB3_5NM_UNI_QSERDES_COM_BIAS_EN_CLKBUFLR_EN		0x044
> > +#define USB3_5NM_UNI_QSERDES_COM_CLK_ENABLE1			0x048
> > +#define USB3_5NM_UNI_QSERDES_COM_SYS_CLK_CTRL			0x04c
> > +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE		0x050
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_EN				0x054
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_IVCO			0x058
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_IETRIM			0x05c
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_IPTRIM			0x060
> > +#define USB3_5NM_UNI_QSERDES_COM_EP_CLOCK_DETECT_CTRL		0x064
> > +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_DET_COMP_STATUS		0x068
> > +#define USB3_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE0		0x06c
> > +#define USB3_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE1		0x070
> > +#define USB3_5NM_UNI_QSERDES_COM_CP_CTRL_MODE0			0x074
> > +#define USB3_5NM_UNI_QSERDES_COM_CP_CTRL_MODE1			0x078
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE0		0x07c
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE1		0x080
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE0		0x084
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE1		0x088
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_CNTRL			0x08c
> > +#define USB3_5NM_UNI_QSERDES_COM_BIAS_EN_CTRL_BY_PSM		0x090
> > +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_EN_SEL			0x094
> > +#define USB3_5NM_UNI_QSERDES_COM_CML_SYSCLK_SEL			0x098
> > +#define USB3_5NM_UNI_QSERDES_COM_RESETSM_CNTRL			0x09c
> > +#define USB3_5NM_UNI_QSERDES_COM_RESETSM_CNTRL2			0x0a0
> > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP_EN			0x0a4
> > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP_CFG			0x0a8
> > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE0		0x0ac
> > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE0		0x0b0
> > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE1		0x0b4
> > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE1		0x0b8
> > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MODE0		0x0bc
> > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE0		0x0c0
> > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MODE1		0x0c4
> > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE1		0x0c8
> > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0		0x0cc
> > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0		0x0d0
> > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0		0x0d4
> > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1		0x0d8
> > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1		0x0dc
> > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1		0x0e0
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_INITVAL		0x0e4
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_EN			0x0e8
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE0		0x0ec
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE0		0x0f0
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE1		0x0f4
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE1		0x0f8
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0		0x0fc
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1		0x100
> > +#define USB3_5NM_UNI_QSERDES_COM_VCOCAL_DEADMAN_CTRL		0x104
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_CTRL			0x108
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAP			0x10c
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE0		0x110
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE0		0x114
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE1		0x118
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE1		0x11c
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL1		0x120
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL2		0x124
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL1		0x128
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL2		0x12c
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL1		0x130
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL2		0x134
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER1		0x138
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER2		0x13c
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_STATUS			0x140
> > +#define USB3_5NM_UNI_QSERDES_COM_RESET_SM_STATUS		0x144
> > +#define USB3_5NM_UNI_QSERDES_COM_RESTRIM_CODE_STATUS		0x148
> > +#define USB3_5NM_UNI_QSERDES_COM_PLLCAL_CODE1_STATUS		0x14c
> > +#define USB3_5NM_UNI_QSERDES_COM_PLLCAL_CODE2_STATUS		0x150
> > +#define USB3_5NM_UNI_QSERDES_COM_CLK_SELECT			0x154
> > +#define USB3_5NM_UNI_QSERDES_COM_HSCLK_SEL			0x158
> > +#define USB3_5NM_UNI_QSERDES_COM_HSCLK_HS_SWITCH_SEL		0x15c
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_BINCODE_STATUS	0x160
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_ANALOG			0x164
> > +#define USB3_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE0		0x168
> > +#define USB3_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE1		0x16c
> > +#define USB3_5NM_UNI_QSERDES_COM_SW_RESET			0x170
> > +#define USB3_5NM_UNI_QSERDES_COM_CORE_CLK_EN			0x174
> > +#define USB3_5NM_UNI_QSERDES_COM_C_READY_STATUS			0x178
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_CONFIG			0x17c
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_RATE_OVERRIDE		0x180
> > +#define USB3_5NM_UNI_QSERDES_COM_SVS_MODE_CLK_SEL		0x184
> > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS0			0x188
> > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS1			0x18c
> > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS2			0x190
> > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS3			0x194
> > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS_SEL			0x198
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_MISC1			0x19c
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_MODE			0x1a0
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_MODE_CONTD			0x1a4
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_DC_LEVEL_CTRL		0x1a8
> > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0x1ac
> > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1b0
> > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0x1b4
> > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1b8
> > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL		0x1bc
> > +#define USB3_5NM_UNI_QSERDES_COM_RESERVED_1			0x1c0
> > +#define USB3_5NM_UNI_QSERDES_COM_MODE_OPERATION_STATUS		0x1c4

these are offset now...

Any reason why this should be 5NM and not use the VX convention we
have...?

> > +
> > +/* Module: USB3_UNI_PHY_QSERDES_TX_PCIE_USB3_UNI_QMP_TX */
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_MODE_LANENO		0x000
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_INVERT			0x004
> > +#define USB3_5NM_UNI_QSERDES_TX_CLKBUF_ENABLE			0x008
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_EMP_POST1_LVL		0x00c
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_IDLE_LVL_LARGE_AMP		0x010
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_DRV_LVL			0x014
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_DRV_LVL_OFFSET		0x018
> > +#define USB3_5NM_UNI_QSERDES_TX_RESET_TSYNC_EN			0x01c
> > +#define USB3_5NM_UNI_QSERDES_TX_PRE_STALL_LDO_BOOST_EN		0x020
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_BAND				0x024
> > +#define USB3_5NM_UNI_QSERDES_TX_SLEW_CNTL			0x028
> > +#define USB3_5NM_UNI_QSERDES_TX_INTERFACE_SELECT		0x02c
> > +#define USB3_5NM_UNI_QSERDES_TX_LPB_EN				0x030
> > +#define USB3_5NM_UNI_QSERDES_TX_RES_CODE_LANE_TX		0x034
> > +#define USB3_5NM_UNI_QSERDES_TX_RES_CODE_LANE_RX		0x038
> > +#define USB3_5NM_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX		0x03c
> > +#define USB3_5NM_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX		0x040
> > +#define USB3_5NM_UNI_QSERDES_TX_PERL_LENGTH1			0x044
> > +#define USB3_5NM_UNI_QSERDES_TX_PERL_LENGTH2			0x048
> > +#define USB3_5NM_UNI_QSERDES_TX_SERDES_BYP_EN_OUT		0x04c
> > +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS_SEL			0x050
> > +#define USB3_5NM_UNI_QSERDES_TX_TRANSCEIVER_BIAS_EN		0x054
> > +#define USB3_5NM_UNI_QSERDES_TX_HIGHZ_DRVR_EN			0x058
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_POL_INV			0x05c
> > +#define USB3_5NM_UNI_QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN	0x060
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN1			0x064
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN2			0x068
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN3			0x06c
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN4			0x070
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN5			0x074
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN6			0x078
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN7			0x07c
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN8			0x080
> > +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_1			0x084
> > +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_2			0x088
> > +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_3			0x08c
> > +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_4			0x090
> > +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_5			0x094
> > +#define USB3_5NM_UNI_QSERDES_TX_ATB_SEL1			0x098
> > +#define USB3_5NM_UNI_QSERDES_TX_ATB_SEL2			0x09c
> > +#define USB3_5NM_UNI_QSERDES_TX_RCV_DETECT_LVL			0x0a0
> > +#define USB3_5NM_UNI_QSERDES_TX_RCV_DETECT_LVL_2		0x0a4
> > +#define USB3_5NM_UNI_QSERDES_TX_PRBS_SEED1			0x0a8
> > +#define USB3_5NM_UNI_QSERDES_TX_PRBS_SEED2			0x0ac
> > +#define USB3_5NM_UNI_QSERDES_TX_PRBS_SEED3			0x0b0
> > +#define USB3_5NM_UNI_QSERDES_TX_PRBS_SEED4			0x0b4
> > +#define USB3_5NM_UNI_QSERDES_TX_RESET_GEN			0x0b8
> > +#define USB3_5NM_UNI_QSERDES_TX_RESET_GEN_MUXES			0x0bc
> > +#define USB3_5NM_UNI_QSERDES_TX_TRAN_DRVR_EMP_EN		0x0c0
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_INTERFACE_MODE		0x0c4
> > +#define USB3_5NM_UNI_QSERDES_TX_VMODE_CTRL1			0x0c8
> > +#define USB3_5NM_UNI_QSERDES_TX_ALOG_OBSV_BUS_CTRL_1		0x0cc
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_STATUS			0x0d0
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_ERROR_COUNT1		0x0d4
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_ERROR_COUNT2		0x0d8
> > +#define USB3_5NM_UNI_QSERDES_TX_ALOG_OBSV_BUS_STATUS_1		0x0dc
> > +#define USB3_5NM_UNI_QSERDES_TX_LANE_DIG_CONFIG			0x0e0
> > +#define USB3_5NM_UNI_QSERDES_TX_PI_QEC_CTRL			0x0e4
> > +#define USB3_5NM_UNI_QSERDES_TX_PRE_EMPH			0x0e8
> > +#define USB3_5NM_UNI_QSERDES_TX_SW_RESET			0x0ec
> > +#define USB3_5NM_UNI_QSERDES_TX_DCC_OFFSET			0x0f0
> > +#define USB3_5NM_UNI_QSERDES_TX_DCC_CMUX_POSTCAL_OFFSET		0x0f4
> > +#define USB3_5NM_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL1		0x0f8
> > +#define USB3_5NM_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL2		0x0fc
> > +#define USB3_5NM_UNI_QSERDES_TX_DIG_BKUP_CTRL			0x100
> > +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS0			0x104
> > +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS1			0x108
> > +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS2			0x10c
> > +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS3			0x110
> > +#define USB3_5NM_UNI_QSERDES_TX_READ_EQCODE			0x114
> > +#define USB3_5NM_UNI_QSERDES_TX_READ_OFFSETCODE			0x118
> > +#define USB3_5NM_UNI_QSERDES_TX_IA_ERROR_COUNTER_LOW		0x11c
> > +#define USB3_5NM_UNI_QSERDES_TX_IA_ERROR_COUNTER_HIGH		0x120
> > +#define USB3_5NM_UNI_QSERDES_TX_VGA_READ_CODE			0x124
> > +#define USB3_5NM_UNI_QSERDES_TX_VTH_READ_CODE			0x128
> > +#define USB3_5NM_UNI_QSERDES_TX_DFE_TAP1_READ_CODE		0x12c
> > +#define USB3_5NM_UNI_QSERDES_TX_DFE_TAP2_READ_CODE		0x130
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_I			0x134
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_IBAR		0x138
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_Q			0x13c
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_QBAR		0x140
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_A			0x144
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_ABAR		0x148
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_SM_ON		0x14c
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_CAL_DONE		0x150
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_SIGNERROR		0x154
> > +#define USB3_5NM_UNI_QSERDES_TX_DCC_CAL_STATUS			0x158
> > +#define USB3_5NM_UNI_QSERDES_TX_DCC_READ_CODE_STATUS		0x15c
> > +
> > +/* Module: USB3_UNI_PHY_QSERDES_RX_QSERDES_RX_PCIE_USB3_UNI_QMP_RX */
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN_HALF		0x000
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN_QUARTER		0x004
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN			0x008
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN_HALF		0x00c
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN_QUARTER		0x010
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN			0x014
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_HALF		0x018
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER	0x01c
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN		0x020
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_HALF		0x024
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER	0x028
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN		0x02c
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN		0x030
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FO_TO_SO_DELAY		0x038
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH	0x040
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_PI_CONTROLS		0x044
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_PI_CTRL2			0x048
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SB2_THRESH1		0x04c
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SB2_THRESH2		0x050
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SB2_GAIN1			0x054
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SB2_GAIN2			0x058
> > +#define USB3_5NM_UNI_QSERDES_RX_AUX_CONTROL			0x05c
> > +#define USB3_5NM_UNI_QSERDES_RX_AUX_DATA_TCOARSE_TFINE		0x060
> > +#define USB3_5NM_UNI_QSERDES_RX_RCLK_AUXDATA_SEL		0x064
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_ENABLE			0x068
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_INITP			0x06c
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_INITN			0x070
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_LVL			0x074
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_MODE			0x078
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_RESET			0x07c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_TERM_BW			0x080
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_RCVR_IQ_EN			0x084
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_I_DC_OFFSETS		0x088
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS		0x08c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_Q_DC_OFFSETS		0x090
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS		0x094
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_A_DC_OFFSETS		0x098
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS		0x09c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_EN			0x0a0
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_ENABLES			0x0a4
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_SIGN			0x0a8
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_HIGHZ_HIGHRATE		0x0ac
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET	0x0b0
> > +#define USB3_5NM_UNI_QSERDES_RX_DFE_1				0x0b4
> > +#define USB3_5NM_UNI_QSERDES_RX_DFE_2				0x0b8
> > +#define USB3_5NM_UNI_QSERDES_RX_DFE_3				0x0bc
> > +#define USB3_5NM_UNI_QSERDES_RX_DFE_4				0x0c0
> > +#define USB3_5NM_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH1		0x0c4
> > +#define USB3_5NM_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH2		0x0c8
> > +#define USB3_5NM_UNI_QSERDES_RX_TX_ADAPT_POST_THRESH		0x0cc
> > +#define USB3_5NM_UNI_QSERDES_RX_TX_ADAPT_MAIN_THRESH		0x0d0
> > +#define USB3_5NM_UNI_QSERDES_RX_VGA_CAL_CNTRL1			0x0d4
> > +#define USB3_5NM_UNI_QSERDES_RX_VGA_CAL_CNTRL2			0x0d8
> > +#define USB3_5NM_UNI_QSERDES_RX_GM_CAL				0x0dc
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_VGA_GAIN2_LSB		0x0e0
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_VGA_GAIN2_MSB		0x0e4
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1		0x0e8
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2		0x0ec
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3		0x0f0
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4		0x0f4
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW		0x0f8
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH		0x0fc
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_MEASURE_TIME		0x100
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_ACCUMULATOR		0x104
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_LSB		0x108
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_MSB		0x10c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x110
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2	0x114
> > +#define USB3_5NM_UNI_QSERDES_RX_SIGDET_ENABLES			0x118
> > +#define USB3_5NM_UNI_QSERDES_RX_SIGDET_CNTRL			0x11c
> > +#define USB3_5NM_UNI_QSERDES_RX_SIGDET_LVL			0x120
> > +#define USB3_5NM_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL		0x124
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_BAND				0x128
> > +#define USB3_5NM_UNI_QSERDES_RX_CDR_FREEZE_UP_DN		0x12c
> > +#define USB3_5NM_UNI_QSERDES_RX_CDR_RESET_OVERRIDE		0x130
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_INTERFACE_MODE		0x134
> > +#define USB3_5NM_UNI_QSERDES_RX_JITTER_GEN_MODE			0x138
> > +#define USB3_5NM_UNI_QSERDES_RX_SJ_AMP1				0x13c
> > +#define USB3_5NM_UNI_QSERDES_RX_SJ_AMP2				0x140
> > +#define USB3_5NM_UNI_QSERDES_RX_SJ_PER1				0x144
> > +#define USB3_5NM_UNI_QSERDES_RX_SJ_PER2				0x148
> > +#define USB3_5NM_UNI_QSERDES_RX_PPM_OFFSET1			0x14c
> > +#define USB3_5NM_UNI_QSERDES_RX_PPM_OFFSET2			0x150
> > +#define USB3_5NM_UNI_QSERDES_RX_SIGN_PPM_PERIOD1		0x154
> > +#define USB3_5NM_UNI_QSERDES_RX_SIGN_PPM_PERIOD2		0x158
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_LOW			0x15c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH			0x160
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH2		0x164
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH3		0x168
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH4		0x16c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_LOW			0x170
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH			0x174
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH2		0x178
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH3		0x17c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH4		0x180
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_LOW			0x184
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH			0x188
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH2		0x18c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH3		0x190
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH4		0x194
> > +#define USB3_5NM_UNI_QSERDES_RX_PHPRE_CTRL			0x198
> > +#define USB3_5NM_UNI_QSERDES_RX_PHPRE_INITVAL			0x19c
> > +#define USB3_5NM_UNI_QSERDES_RX_DFE_EN_TIMER			0x1a0
> > +#define USB3_5NM_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET	0x1a4
> > +#define USB3_5NM_UNI_QSERDES_RX_DCC_CTRL1			0x1a8
> > +#define USB3_5NM_UNI_QSERDES_RX_DCC_CTRL2			0x1ac
> > +#define USB3_5NM_UNI_QSERDES_RX_VTH_CODE			0x1b0
> > +#define USB3_5NM_UNI_QSERDES_RX_VTH_MIN_THRESH			0x1b4
> > +#define USB3_5NM_UNI_QSERDES_RX_VTH_MAX_THRESH			0x1b8
> > +#define USB3_5NM_UNI_QSERDES_RX_ALOG_OBSV_BUS_CTRL_1		0x1bc
> > +#define USB3_5NM_UNI_QSERDES_RX_PI_CTRL1			0x1c0
> > +#define USB3_5NM_UNI_QSERDES_RX_PI_CTRL2			0x1c4
> > +#define USB3_5NM_UNI_QSERDES_RX_PI_QUAD				0x1c8
> > +#define USB3_5NM_UNI_QSERDES_RX_IDATA1				0x1cc
> > +#define USB3_5NM_UNI_QSERDES_RX_IDATA2				0x1d0
> > +#define USB3_5NM_UNI_QSERDES_RX_AUX_DATA1			0x1d4
> > +#define USB3_5NM_UNI_QSERDES_RX_AUX_DATA2			0x1d8
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_OUTP			0x1dc
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_OUTN			0x1e0
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_SIGDET			0x1e4
> > +#define USB3_5NM_UNI_QSERDES_RX_ALOG_OBSV_BUS_STATUS_1		0x1e8
> > +
> > +/* Module:  USB3_UNI_PCS_LN_PCIE_USB3_UNI_PCS_LANE */
> > +#define USB3_5NM_UNI_PCS_LN_PCS_STATUS1				0x00
> > +#define USB3_5NM_UNI_PCS_LN_PCS_STATUS2				0x04
> > +#define USB3_5NM_UNI_PCS_LN_PCS_STATUS2_CLEAR			0x08
> > +#define USB3_5NM_UNI_PCS_LN_PCS_STATUS3				0x0c
> > +#define USB3_5NM_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS		0x10
> > +#define USB3_5NM_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS		0x14
> > +#define USB3_5NM_UNI_PCS_LN_BIST_CHK_STATUS			0x18
> > +#define USB3_5NM_UNI_PCS_LN_INSIG_SW_CTRL1			0x1c
> > +#define USB3_5NM_UNI_PCS_LN_INSIG_MX_CTRL1			0x20
> > +#define USB3_5NM_UNI_PCS_LN_OUTSIG_SW_CTRL1			0x24
> > +#define USB3_5NM_UNI_PCS_LN_OUTSIG_MX_CTRL1			0x28
> > +#define USB3_5NM_UNI_PCS_LN_TEST_CONTROL1			0x2c
> > +#define USB3_5NM_UNI_PCS_LN_BIST_CTRL				0x30
> > +#define USB3_5NM_UNI_PCS_LN_PRBS_SEED0				0x34
> > +#define USB3_5NM_UNI_PCS_LN_PRBS_SEED1				0x38
> > +#define USB3_5NM_UNI_PCS_LN_FIXED_PAT_CTRL			0x3c
> > +#define USB3_5NM_UNI_PCS_LN_EQ_CONFIG				0x40
> > +#define USB3_5NM_UNI_PCS_LN_TEST_CONTROL2			0x44
> > +#define USB3_5NM_UNI_PCS_LN_TEST_CONTROL3			0x48
> > +
> > +/* Module: USB3_UNI_PCS_PCIE_LN_PCIE_USB3_UNI_PCS_PCIE_LANE */
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST	0x00
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST_RS	0x04
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_EN		0x08
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_DSBL_L			0x0c
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_DSBL_H			0x10
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_LANE_OFF_CONFIG		0x14
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG1		0x18
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG2		0x1c
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_PCIE_PCS_STATUS		0x20
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_INSIG_SW_CTRL2			0x24
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_INSIG_MX_CTRL2			0x28
> > +
> > +/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS */
> > +#define USB3_5NM_UNI_PCS_SW_RESET				0x000
> > +#define USB3_5NM_UNI_PCS_REVISION_ID0				0x004
> > +#define USB3_5NM_UNI_PCS_REVISION_ID1				0x008
> > +#define USB3_5NM_UNI_PCS_REVISION_ID2				0x00c
> > +#define USB3_5NM_UNI_PCS_REVISION_ID3				0x010
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS1				0x014
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS2				0x018
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS3				0x01c
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS4				0x020
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS5				0x024
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS6				0x028
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS7				0x02c
> > +#define USB3_5NM_UNI_PCS_DEBUG_BUS_0_STATUS			0x030
> > +#define USB3_5NM_UNI_PCS_DEBUG_BUS_1_STATUS			0x034
> > +#define USB3_5NM_UNI_PCS_DEBUG_BUS_2_STATUS			0x038
> > +#define USB3_5NM_UNI_PCS_DEBUG_BUS_3_STATUS			0x03c
> > +#define USB3_5NM_UNI_PCS_POWER_DOWN_CONTROL			0x040
> > +#define USB3_5NM_UNI_PCS_START_CONTROL				0x044
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL1				0x048
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL2				0x04c
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL3				0x050
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL4				0x054
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL5				0x058
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL6				0x05c
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL7				0x060
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL8				0x064
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL1				0x068
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL2				0x06c
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL3				0x070
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL4				0x074
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL5				0x078
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL7				0x07c
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL8				0x080
> > +#define USB3_5NM_UNI_PCS_OUTSIG_SW_CTRL1			0x084
> > +#define USB3_5NM_UNI_PCS_OUTSIG_MX_CTRL1			0x088
> > +#define USB3_5NM_UNI_PCS_CLAMP_ENABLE				0x08c
> > +#define USB3_5NM_UNI_PCS_POWER_STATE_CONFIG1			0x090
> > +#define USB3_5NM_UNI_PCS_POWER_STATE_CONFIG2			0x094
> > +#define USB3_5NM_UNI_PCS_FLL_CNTRL1				0x098
> > +#define USB3_5NM_UNI_PCS_FLL_CNTRL2				0x09c
> > +#define USB3_5NM_UNI_PCS_FLL_CNT_VAL_L				0x0a0
> > +#define USB3_5NM_UNI_PCS_FLL_CNT_VAL_H_TOL			0x0a4
> > +#define USB3_5NM_UNI_PCS_FLL_MAN_CODE				0x0a8
> > +#define USB3_5NM_UNI_PCS_TEST_CONTROL1				0x0ac
> > +#define USB3_5NM_UNI_PCS_TEST_CONTROL2				0x0b0
> > +#define USB3_5NM_UNI_PCS_TEST_CONTROL3				0x0b4
> > +#define USB3_5NM_UNI_PCS_TEST_CONTROL4				0x0b8
> > +#define USB3_5NM_UNI_PCS_TEST_CONTROL5				0x0bc
> > +#define USB3_5NM_UNI_PCS_TEST_CONTROL6				0x0c0
> > +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG1			0x0c4
> > +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG2			0x0c8
> > +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG3			0x0cc
> > +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG4			0x0d0
> > +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG5			0x0d4
> > +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG6			0x0d8
> > +#define USB3_5NM_UNI_PCS_REFGEN_REQ_CONFIG1			0x0dc
> > +#define USB3_5NM_UNI_PCS_REFGEN_REQ_CONFIG2			0x0e0
> > +#define USB3_5NM_UNI_PCS_REFGEN_REQ_CONFIG3			0x0e4
> > +#define USB3_5NM_UNI_PCS_BIST_CTRL				0x0e8
> > +#define USB3_5NM_UNI_PCS_PRBS_POLY0				0x0ec
> > +#define USB3_5NM_UNI_PCS_PRBS_POLY1				0x0f0
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT0				0x0f4
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT1				0x0f8
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT2				0x0fc
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT3				0x100
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT4				0x104
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT5				0x108
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT6				0x10c
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT7				0x110
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT8				0x114
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT9				0x118
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT10				0x11c
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT11				0x120
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT12				0x124
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT13				0x128
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT14				0x12c
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT15				0x130
> > +#define USB3_5NM_UNI_PCS_TXMGN_CONFIG				0x134
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V0				0x138
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V1				0x13c
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V2				0x140
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V3				0x144
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V4				0x148
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V0_RS			0x14c
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V1_RS			0x150
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V2_RS			0x154
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V3_RS			0x158
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V4_RS			0x15c
> > +#define USB3_5NM_UNI_PCS_G3S2_TXMGN_MAIN			0x160
> > +#define USB3_5NM_UNI_PCS_G3S2_TXMGN_MAIN_RS			0x164
> > +#define USB3_5NM_UNI_PCS_G12S1_TXDEEMPH_M6DB			0x168
> > +#define USB3_5NM_UNI_PCS_G12S1_TXDEEMPH_M3P5DB			0x16c
> > +#define USB3_5NM_UNI_PCS_G3S2_PRE_GAIN				0x170
> > +#define USB3_5NM_UNI_PCS_G3S2_POST_GAIN				0x174
> > +#define USB3_5NM_UNI_PCS_G3S2_PRE_POST_OFFSET			0x178
> > +#define USB3_5NM_UNI_PCS_G3S2_PRE_GAIN_RS			0x17c
> > +#define USB3_5NM_UNI_PCS_G3S2_POST_GAIN_RS			0x180
> > +#define USB3_5NM_UNI_PCS_G3S2_PRE_POST_OFFSET_RS		0x184
> > +#define USB3_5NM_UNI_PCS_RX_SIGDET_LVL				0x188
> > +#define USB3_5NM_UNI_PCS_RX_SIGDET_DTCT_CNTRL			0x18c
> > +#define USB3_5NM_UNI_PCS_RCVR_DTCT_DLY_P1U2_L			0x190
> > +#define USB3_5NM_UNI_PCS_RCVR_DTCT_DLY_P1U2_H			0x194
> > +#define USB3_5NM_UNI_PCS_RATE_SLEW_CNTRL1			0x198
> > +#define USB3_5NM_UNI_PCS_RATE_SLEW_CNTRL2			0x19c
> > +#define USB3_5NM_UNI_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x1a0
> > +#define USB3_5NM_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L		0x1a4
> > +#define USB3_5NM_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H		0x1a8
> > +#define USB3_5NM_UNI_PCS_TSYNC_RSYNC_TIME			0x1ac
> > +#define USB3_5NM_UNI_PCS_CDR_RESET_TIME				0x1b0
> > +#define USB3_5NM_UNI_PCS_TSYNC_DLY_TIME				0x1b4
> > +#define USB3_5NM_UNI_PCS_ELECIDLE_DLY_SEL			0x1b8
> > +#define USB3_5NM_UNI_PCS_CMN_ACK_OUT_SEL			0x1bc
> > +#define USB3_5NM_UNI_PCS_ALIGN_DETECT_CONFIG1			0x1c0
> > +#define USB3_5NM_UNI_PCS_ALIGN_DETECT_CONFIG2			0x1c4
> > +#define USB3_5NM_UNI_PCS_ALIGN_DETECT_CONFIG3			0x1c8
> > +#define USB3_5NM_UNI_PCS_ALIGN_DETECT_CONFIG4			0x1cc
> > +#define USB3_5NM_UNI_PCS_PCS_TX_RX_CONFIG			0x1d0
> > +#define USB3_5NM_UNI_PCS_RX_IDLE_DTCT_CNTRL			0x1d4
> > +#define USB3_5NM_UNI_PCS_RX_DCC_CAL_CONFIG			0x1d8
> > +#define USB3_5NM_UNI_PCS_EQ_CONFIG1				0x1dc
> > +#define USB3_5NM_UNI_PCS_EQ_CONFIG2				0x1e0
> > +#define USB3_5NM_UNI_PCS_EQ_CONFIG3				0x1e4
> > +#define USB3_5NM_UNI_PCS_EQ_CONFIG4				0x1e8
> > +#define USB3_5NM_UNI_PCS_EQ_CONFIG5				0x1ec
> > +
> > +/* Module: USB3_UNI_PHY_PCIE_PCS */
> > +#define USB3_5NM_UNI_PCS_PCIE_INT_AUX_CLK_STATUS		0x00
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_STATUS			0x04
> > +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG1		0x08
> > +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG2		0x0c
> > +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG3		0x10
> > +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG4		0x14
> > +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG5		0x18
> > +#define USB3_5NM_UNI_PCS_PCIE_PCS_TX_RX_CONFIG			0x1c
> > +#define USB3_5NM_UNI_PCS_PCIE_ENDPOINT_REFCLK_DRIVE		0x20
> > +#define USB3_5NM_UNI_PCS_PCIE_ENDPOINT_REFCLK_CNTRL		0x24
> > +#define USB3_5NM_UNI_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK	0x28
> > +#define USB3_5NM_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L		0x2c
> > +#define USB3_5NM_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H		0x30
> > +#define USB3_5NM_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL1		0x34
> > +#define USB3_5NM_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL2		0x38
> > +#define USB3_5NM_UNI_PCS_PCIE_SIGDET_CNTRL			0x3c
> > +#define USB3_5NM_UNI_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME		0x40
> > +#define USB3_5NM_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L	0x44
> > +#define USB3_5NM_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H	0x48
> > +#define USB3_5NM_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L	0x4c
> > +#define USB3_5NM_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H	0x50
> > +#define USB3_5NM_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG1		0x54
> > +#define USB3_5NM_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG2		0x58
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG1			0x5c
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG2			0x60
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG3			0x64
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG4			0x68
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG5			0x6c
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG6			0x70
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG7			0x74
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1		0x78
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2		0x7c
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3		0x80
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4		0x84
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5		0x88
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6		0x8c
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7		0x90
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_ACTIONS			0x94
> > +#define USB3_5NM_UNI_PCS_PCIE_LOCAL_FS				0x98
> > +#define USB3_5NM_UNI_PCS_PCIE_LOCAL_LF				0x9c
> > +#define USB3_5NM_UNI_PCS_PCIE_LOCAL_FS_RS			0xa0
> > +#define USB3_5NM_UNI_PCS_PCIE_EQ_CONFIG1			0xa4
> > +#define USB3_5NM_UNI_PCS_PCIE_EQ_CONFIG2			0xa8
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P0_P1_PRE			0xac
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P2_P3_PRE			0xb0
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P4_P5_PRE			0xb4
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P6_P7_PRE			0xb8
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P8_P9_PRE			0xbc
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P10_PRE			0xc0
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P1_P3_PRE_RS		0xc4
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P4_P5_PRE_RS		0xc8
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P6_P9_PRE_RS		0xcc
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P0_P1_POST			0xd0
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P2_P3_POST			0xd4
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P4_P5_POST			0xd8
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P6_P7_POST			0xdc
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P8_P9_POST			0xe0
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P10_POST			0xe4
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P1_P3_POST_RS		0xe8
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P4_P5_POST_RS		0xec
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P6_P9_POST_RS		0xf0
> > +#define USB3_5NM_UNI_PCS_PCIE_RXEQEVAL_TIME			0xf4
> > +
> > +/* Module: USB3_UNI_PHY_PCIE_PCS_DEBUG_INTGEN */
> > +#define USB3_5NM_UNI_PCS_INTGEN_INTGEN_STATUS1			0x00
> > +#define USB3_5NM_UNI_PCS_INTGEN_INTGEN_STATUS2			0x04
> > +#define USB3_5NM_UNI_PCS_INTGEN_CONFIG1				0x08
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG1		0x0c
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG2		0x10
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG3		0x14
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG4		0x18
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG5		0x1c
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG1		0x20
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG2		0x24
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG3		0x28
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG4		0x2c
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG5		0x30
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG1		0x34
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG2		0x38
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG3		0x3c
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG4		0x40
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG5		0x44
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG1		0x48
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG2		0x4c
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG3		0x50
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG4		0x54
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG5		0x58
> > +
> > +
> > +/* Module: USB3_UNI_PCS_USB3_PCIE_USB3_UNI_PCS_USB3 */
> > +#define USB3_5NM_UNI_PCS_USB3_POWER_STATE_CONFIG1		0x00
> > +#define USB3_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS		0x04
> > +#define USB3_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL		0x08
> > +#define USB3_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL2		0x0c
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS	0x10
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR		0x14
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL		0x18
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_TX_ECSTART			0x1c
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_PER_TIMER_VAL		0x20
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_TX_END_CNT_U3_START		0x24
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_CONFIG1			0x28
> > +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_LOCK_TIME		0x2c
> > +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME		0x30
> > +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_CTLE_TIME		0x34
> > +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2		0x38
> > +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2		0x3c
> > +#define USB3_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L		0x40
> > +#define USB3_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H		0x44
> > +#define USB3_5NM_UNI_PCS_USB3_ARCVR_DTCT_EN_PERIOD		0x48
> > +#define USB3_5NM_UNI_PCS_USB3_ARCVR_DTCT_CM_DLY			0x4c
> > +#define USB3_5NM_UNI_PCS_USB3_TXONESZEROS_RUN_LENGTH		0x50
> > +#define USB3_5NM_UNI_PCS_USB3_ALFPS_DEGLITCH_VAL		0x54
> > +#define USB3_5NM_UNI_PCS_USB3_SIGDET_STARTUP_TIMER_VAL		0x58
> > +#define USB3_5NM_UNI_PCS_USB3_TEST_CONTROL			0x5c
> > +#define USB3_5NM_UNI_PCS_USB3_RXTERMINATION_DLY_SEL		0x60
> > +
> > +#endif
> > -- 
> > 2.35.1
> 
> -- 
> ~Vinod

On Tue 17 May 03:31 PDT 2022, Vinod Koul wrote:

> On 13-05-22, 15:53, Bjorn Andersson wrote:
> > Add all registers defines from qcom,usb3-5nm-qmp-uni.h of the msm-5.4
> > kernel. Offsets are adjusted to be relative to each sub-block, as we
> > describe the individual pieces in the upstream kernel and "5NM" are
> > injected in the defines to not collide with existing constants.
> > 
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> >  .../phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h  | 617 ++++++++++++++++++
> >  1 file changed, 617 insertions(+)
> >  create mode 100644 drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> > 
> > diff --git a/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> > new file mode 100644
> > index 000000000000..b912e50825f9
> > --- /dev/null
> > +++ b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> > @@ -0,0 +1,617 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> 
> should this be 2022 or add Linaro one for 2022..?
> 

I thought about it, but Qualcomm produced this with the 2020 copyright
and I didn't change anything copyrightable.

Regards,
Bjorn

> > + */
> > +
> > +#ifndef PHY_QCOM_USB3_5NM_QMP_UNI_H_
> > +#define PHY_QCOM_USB3_5NM_QMP_UNI_H_
> > +
> > +/* Module: USB3_UNI_PHY_QSERDES_COM_QSERDES_COM_PCIE_USB3_UNI_QMP_PLL */
> > +#define USB3_5NM_UNI_QSERDES_COM_ATB_SEL1			0x000
> > +#define USB3_5NM_UNI_QSERDES_COM_ATB_SEL2			0x004
> > +#define USB3_5NM_UNI_QSERDES_COM_FREQ_UPDATE			0x008
> > +#define USB3_5NM_UNI_QSERDES_COM_BG_TIMER			0x00c
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_EN_CENTER			0x010
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_ADJ_PER1			0x014
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_ADJ_PER2			0x018
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_PER1			0x01c
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_PER2			0x020
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0		0x024
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0		0x028
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE0		0x02c
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1		0x030
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1		0x034
> > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE1		0x038
> > +#define USB3_5NM_UNI_QSERDES_COM_POST_DIV			0x03c
> > +#define USB3_5NM_UNI_QSERDES_COM_POST_DIV_MUX			0x040
> > +#define USB3_5NM_UNI_QSERDES_COM_BIAS_EN_CLKBUFLR_EN		0x044
> > +#define USB3_5NM_UNI_QSERDES_COM_CLK_ENABLE1			0x048
> > +#define USB3_5NM_UNI_QSERDES_COM_SYS_CLK_CTRL			0x04c
> > +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE		0x050
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_EN				0x054
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_IVCO			0x058
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_IETRIM			0x05c
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_IPTRIM			0x060
> > +#define USB3_5NM_UNI_QSERDES_COM_EP_CLOCK_DETECT_CTRL		0x064
> > +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_DET_COMP_STATUS		0x068
> > +#define USB3_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE0		0x06c
> > +#define USB3_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE1		0x070
> > +#define USB3_5NM_UNI_QSERDES_COM_CP_CTRL_MODE0			0x074
> > +#define USB3_5NM_UNI_QSERDES_COM_CP_CTRL_MODE1			0x078
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE0		0x07c
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE1		0x080
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE0		0x084
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE1		0x088
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_CNTRL			0x08c
> > +#define USB3_5NM_UNI_QSERDES_COM_BIAS_EN_CTRL_BY_PSM		0x090
> > +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_EN_SEL			0x094
> > +#define USB3_5NM_UNI_QSERDES_COM_CML_SYSCLK_SEL			0x098
> > +#define USB3_5NM_UNI_QSERDES_COM_RESETSM_CNTRL			0x09c
> > +#define USB3_5NM_UNI_QSERDES_COM_RESETSM_CNTRL2			0x0a0
> > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP_EN			0x0a4
> > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP_CFG			0x0a8
> > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE0		0x0ac
> > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE0		0x0b0
> > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE1		0x0b4
> > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE1		0x0b8
> > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MODE0		0x0bc
> > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE0		0x0c0
> > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MODE1		0x0c4
> > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE1		0x0c8
> > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0		0x0cc
> > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0		0x0d0
> > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0		0x0d4
> > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1		0x0d8
> > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1		0x0dc
> > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1		0x0e0
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_INITVAL		0x0e4
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_EN			0x0e8
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE0		0x0ec
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE0		0x0f0
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE1		0x0f4
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE1		0x0f8
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0		0x0fc
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1		0x100
> > +#define USB3_5NM_UNI_QSERDES_COM_VCOCAL_DEADMAN_CTRL		0x104
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_CTRL			0x108
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAP			0x10c
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE0		0x110
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE0		0x114
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE1		0x118
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE1		0x11c
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL1		0x120
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL2		0x124
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL1		0x128
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL2		0x12c
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL1		0x130
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL2		0x134
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER1		0x138
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER2		0x13c
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_STATUS			0x140
> > +#define USB3_5NM_UNI_QSERDES_COM_RESET_SM_STATUS		0x144
> > +#define USB3_5NM_UNI_QSERDES_COM_RESTRIM_CODE_STATUS		0x148
> > +#define USB3_5NM_UNI_QSERDES_COM_PLLCAL_CODE1_STATUS		0x14c
> > +#define USB3_5NM_UNI_QSERDES_COM_PLLCAL_CODE2_STATUS		0x150
> > +#define USB3_5NM_UNI_QSERDES_COM_CLK_SELECT			0x154
> > +#define USB3_5NM_UNI_QSERDES_COM_HSCLK_SEL			0x158
> > +#define USB3_5NM_UNI_QSERDES_COM_HSCLK_HS_SWITCH_SEL		0x15c
> > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_BINCODE_STATUS	0x160
> > +#define USB3_5NM_UNI_QSERDES_COM_PLL_ANALOG			0x164
> > +#define USB3_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE0		0x168
> > +#define USB3_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE1		0x16c
> > +#define USB3_5NM_UNI_QSERDES_COM_SW_RESET			0x170
> > +#define USB3_5NM_UNI_QSERDES_COM_CORE_CLK_EN			0x174
> > +#define USB3_5NM_UNI_QSERDES_COM_C_READY_STATUS			0x178
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_CONFIG			0x17c
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_RATE_OVERRIDE		0x180
> > +#define USB3_5NM_UNI_QSERDES_COM_SVS_MODE_CLK_SEL		0x184
> > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS0			0x188
> > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS1			0x18c
> > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS2			0x190
> > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS3			0x194
> > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS_SEL			0x198
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_MISC1			0x19c
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_MODE			0x1a0
> > +#define USB3_5NM_UNI_QSERDES_COM_CMN_MODE_CONTD			0x1a4
> > +#define USB3_5NM_UNI_QSERDES_COM_VCO_DC_LEVEL_CTRL		0x1a8
> > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0x1ac
> > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1b0
> > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0x1b4
> > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1b8
> > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL		0x1bc
> > +#define USB3_5NM_UNI_QSERDES_COM_RESERVED_1			0x1c0
> > +#define USB3_5NM_UNI_QSERDES_COM_MODE_OPERATION_STATUS		0x1c4
> > +
> > +/* Module: USB3_UNI_PHY_QSERDES_TX_PCIE_USB3_UNI_QMP_TX */
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_MODE_LANENO		0x000
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_INVERT			0x004
> > +#define USB3_5NM_UNI_QSERDES_TX_CLKBUF_ENABLE			0x008
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_EMP_POST1_LVL		0x00c
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_IDLE_LVL_LARGE_AMP		0x010
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_DRV_LVL			0x014
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_DRV_LVL_OFFSET		0x018
> > +#define USB3_5NM_UNI_QSERDES_TX_RESET_TSYNC_EN			0x01c
> > +#define USB3_5NM_UNI_QSERDES_TX_PRE_STALL_LDO_BOOST_EN		0x020
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_BAND				0x024
> > +#define USB3_5NM_UNI_QSERDES_TX_SLEW_CNTL			0x028
> > +#define USB3_5NM_UNI_QSERDES_TX_INTERFACE_SELECT		0x02c
> > +#define USB3_5NM_UNI_QSERDES_TX_LPB_EN				0x030
> > +#define USB3_5NM_UNI_QSERDES_TX_RES_CODE_LANE_TX		0x034
> > +#define USB3_5NM_UNI_QSERDES_TX_RES_CODE_LANE_RX		0x038
> > +#define USB3_5NM_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX		0x03c
> > +#define USB3_5NM_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX		0x040
> > +#define USB3_5NM_UNI_QSERDES_TX_PERL_LENGTH1			0x044
> > +#define USB3_5NM_UNI_QSERDES_TX_PERL_LENGTH2			0x048
> > +#define USB3_5NM_UNI_QSERDES_TX_SERDES_BYP_EN_OUT		0x04c
> > +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS_SEL			0x050
> > +#define USB3_5NM_UNI_QSERDES_TX_TRANSCEIVER_BIAS_EN		0x054
> > +#define USB3_5NM_UNI_QSERDES_TX_HIGHZ_DRVR_EN			0x058
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_POL_INV			0x05c
> > +#define USB3_5NM_UNI_QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN	0x060
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN1			0x064
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN2			0x068
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN3			0x06c
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN4			0x070
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN5			0x074
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN6			0x078
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN7			0x07c
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_PATTERN8			0x080
> > +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_1			0x084
> > +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_2			0x088
> > +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_3			0x08c
> > +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_4			0x090
> > +#define USB3_5NM_UNI_QSERDES_TX_LANE_MODE_5			0x094
> > +#define USB3_5NM_UNI_QSERDES_TX_ATB_SEL1			0x098
> > +#define USB3_5NM_UNI_QSERDES_TX_ATB_SEL2			0x09c
> > +#define USB3_5NM_UNI_QSERDES_TX_RCV_DETECT_LVL			0x0a0
> > +#define USB3_5NM_UNI_QSERDES_TX_RCV_DETECT_LVL_2		0x0a4
> > +#define USB3_5NM_UNI_QSERDES_TX_PRBS_SEED1			0x0a8
> > +#define USB3_5NM_UNI_QSERDES_TX_PRBS_SEED2			0x0ac
> > +#define USB3_5NM_UNI_QSERDES_TX_PRBS_SEED3			0x0b0
> > +#define USB3_5NM_UNI_QSERDES_TX_PRBS_SEED4			0x0b4
> > +#define USB3_5NM_UNI_QSERDES_TX_RESET_GEN			0x0b8
> > +#define USB3_5NM_UNI_QSERDES_TX_RESET_GEN_MUXES			0x0bc
> > +#define USB3_5NM_UNI_QSERDES_TX_TRAN_DRVR_EMP_EN		0x0c0
> > +#define USB3_5NM_UNI_QSERDES_TX_TX_INTERFACE_MODE		0x0c4
> > +#define USB3_5NM_UNI_QSERDES_TX_VMODE_CTRL1			0x0c8
> > +#define USB3_5NM_UNI_QSERDES_TX_ALOG_OBSV_BUS_CTRL_1		0x0cc
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_STATUS			0x0d0
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_ERROR_COUNT1		0x0d4
> > +#define USB3_5NM_UNI_QSERDES_TX_BIST_ERROR_COUNT2		0x0d8
> > +#define USB3_5NM_UNI_QSERDES_TX_ALOG_OBSV_BUS_STATUS_1		0x0dc
> > +#define USB3_5NM_UNI_QSERDES_TX_LANE_DIG_CONFIG			0x0e0
> > +#define USB3_5NM_UNI_QSERDES_TX_PI_QEC_CTRL			0x0e4
> > +#define USB3_5NM_UNI_QSERDES_TX_PRE_EMPH			0x0e8
> > +#define USB3_5NM_UNI_QSERDES_TX_SW_RESET			0x0ec
> > +#define USB3_5NM_UNI_QSERDES_TX_DCC_OFFSET			0x0f0
> > +#define USB3_5NM_UNI_QSERDES_TX_DCC_CMUX_POSTCAL_OFFSET		0x0f4
> > +#define USB3_5NM_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL1		0x0f8
> > +#define USB3_5NM_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL2		0x0fc
> > +#define USB3_5NM_UNI_QSERDES_TX_DIG_BKUP_CTRL			0x100
> > +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS0			0x104
> > +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS1			0x108
> > +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS2			0x10c
> > +#define USB3_5NM_UNI_QSERDES_TX_DEBUG_BUS3			0x110
> > +#define USB3_5NM_UNI_QSERDES_TX_READ_EQCODE			0x114
> > +#define USB3_5NM_UNI_QSERDES_TX_READ_OFFSETCODE			0x118
> > +#define USB3_5NM_UNI_QSERDES_TX_IA_ERROR_COUNTER_LOW		0x11c
> > +#define USB3_5NM_UNI_QSERDES_TX_IA_ERROR_COUNTER_HIGH		0x120
> > +#define USB3_5NM_UNI_QSERDES_TX_VGA_READ_CODE			0x124
> > +#define USB3_5NM_UNI_QSERDES_TX_VTH_READ_CODE			0x128
> > +#define USB3_5NM_UNI_QSERDES_TX_DFE_TAP1_READ_CODE		0x12c
> > +#define USB3_5NM_UNI_QSERDES_TX_DFE_TAP2_READ_CODE		0x130
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_I			0x134
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_IBAR		0x138
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_Q			0x13c
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_QBAR		0x140
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_A			0x144
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_ABAR		0x148
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_SM_ON		0x14c
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_CAL_DONE		0x150
> > +#define USB3_5NM_UNI_QSERDES_TX_IDAC_STATUS_SIGNERROR		0x154
> > +#define USB3_5NM_UNI_QSERDES_TX_DCC_CAL_STATUS			0x158
> > +#define USB3_5NM_UNI_QSERDES_TX_DCC_READ_CODE_STATUS		0x15c
> > +
> > +/* Module: USB3_UNI_PHY_QSERDES_RX_QSERDES_RX_PCIE_USB3_UNI_QMP_RX */
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN_HALF		0x000
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN_QUARTER		0x004
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FO_GAIN			0x008
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN_HALF		0x00c
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN_QUARTER		0x010
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SO_GAIN			0x014
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_HALF		0x018
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER	0x01c
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN		0x020
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_HALF		0x024
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER	0x028
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN		0x02c
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN		0x030
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FO_TO_SO_DELAY		0x038
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH	0x040
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_PI_CONTROLS		0x044
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_PI_CTRL2			0x048
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SB2_THRESH1		0x04c
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SB2_THRESH2		0x050
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SB2_GAIN1			0x054
> > +#define USB3_5NM_UNI_QSERDES_RX_UCDR_SB2_GAIN2			0x058
> > +#define USB3_5NM_UNI_QSERDES_RX_AUX_CONTROL			0x05c
> > +#define USB3_5NM_UNI_QSERDES_RX_AUX_DATA_TCOARSE_TFINE		0x060
> > +#define USB3_5NM_UNI_QSERDES_RX_RCLK_AUXDATA_SEL		0x064
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_ENABLE			0x068
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_INITP			0x06c
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_INITN			0x070
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_LVL			0x074
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_MODE			0x078
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_RESET			0x07c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_TERM_BW			0x080
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_RCVR_IQ_EN			0x084
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_I_DC_OFFSETS		0x088
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS		0x08c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_Q_DC_OFFSETS		0x090
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS		0x094
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_A_DC_OFFSETS		0x098
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS		0x09c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_EN			0x0a0
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_ENABLES			0x0a4
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_SIGN			0x0a8
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_HIGHZ_HIGHRATE		0x0ac
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET	0x0b0
> > +#define USB3_5NM_UNI_QSERDES_RX_DFE_1				0x0b4
> > +#define USB3_5NM_UNI_QSERDES_RX_DFE_2				0x0b8
> > +#define USB3_5NM_UNI_QSERDES_RX_DFE_3				0x0bc
> > +#define USB3_5NM_UNI_QSERDES_RX_DFE_4				0x0c0
> > +#define USB3_5NM_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH1		0x0c4
> > +#define USB3_5NM_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH2		0x0c8
> > +#define USB3_5NM_UNI_QSERDES_RX_TX_ADAPT_POST_THRESH		0x0cc
> > +#define USB3_5NM_UNI_QSERDES_RX_TX_ADAPT_MAIN_THRESH		0x0d0
> > +#define USB3_5NM_UNI_QSERDES_RX_VGA_CAL_CNTRL1			0x0d4
> > +#define USB3_5NM_UNI_QSERDES_RX_VGA_CAL_CNTRL2			0x0d8
> > +#define USB3_5NM_UNI_QSERDES_RX_GM_CAL				0x0dc
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_VGA_GAIN2_LSB		0x0e0
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_VGA_GAIN2_MSB		0x0e4
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1		0x0e8
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2		0x0ec
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3		0x0f0
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4		0x0f4
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW		0x0f8
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH		0x0fc
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_MEASURE_TIME		0x100
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_IDAC_ACCUMULATOR		0x104
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_LSB		0x108
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_MSB		0x10c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x110
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2	0x114
> > +#define USB3_5NM_UNI_QSERDES_RX_SIGDET_ENABLES			0x118
> > +#define USB3_5NM_UNI_QSERDES_RX_SIGDET_CNTRL			0x11c
> > +#define USB3_5NM_UNI_QSERDES_RX_SIGDET_LVL			0x120
> > +#define USB3_5NM_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL		0x124
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_BAND				0x128
> > +#define USB3_5NM_UNI_QSERDES_RX_CDR_FREEZE_UP_DN		0x12c
> > +#define USB3_5NM_UNI_QSERDES_RX_CDR_RESET_OVERRIDE		0x130
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_INTERFACE_MODE		0x134
> > +#define USB3_5NM_UNI_QSERDES_RX_JITTER_GEN_MODE			0x138
> > +#define USB3_5NM_UNI_QSERDES_RX_SJ_AMP1				0x13c
> > +#define USB3_5NM_UNI_QSERDES_RX_SJ_AMP2				0x140
> > +#define USB3_5NM_UNI_QSERDES_RX_SJ_PER1				0x144
> > +#define USB3_5NM_UNI_QSERDES_RX_SJ_PER2				0x148
> > +#define USB3_5NM_UNI_QSERDES_RX_PPM_OFFSET1			0x14c
> > +#define USB3_5NM_UNI_QSERDES_RX_PPM_OFFSET2			0x150
> > +#define USB3_5NM_UNI_QSERDES_RX_SIGN_PPM_PERIOD1		0x154
> > +#define USB3_5NM_UNI_QSERDES_RX_SIGN_PPM_PERIOD2		0x158
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_LOW			0x15c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH			0x160
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH2		0x164
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH3		0x168
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_00_HIGH4		0x16c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_LOW			0x170
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH			0x174
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH2		0x178
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH3		0x17c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_01_HIGH4		0x180
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_LOW			0x184
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH			0x188
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH2		0x18c
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH3		0x190
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_MODE_10_HIGH4		0x194
> > +#define USB3_5NM_UNI_QSERDES_RX_PHPRE_CTRL			0x198
> > +#define USB3_5NM_UNI_QSERDES_RX_PHPRE_INITVAL			0x19c
> > +#define USB3_5NM_UNI_QSERDES_RX_DFE_EN_TIMER			0x1a0
> > +#define USB3_5NM_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET	0x1a4
> > +#define USB3_5NM_UNI_QSERDES_RX_DCC_CTRL1			0x1a8
> > +#define USB3_5NM_UNI_QSERDES_RX_DCC_CTRL2			0x1ac
> > +#define USB3_5NM_UNI_QSERDES_RX_VTH_CODE			0x1b0
> > +#define USB3_5NM_UNI_QSERDES_RX_VTH_MIN_THRESH			0x1b4
> > +#define USB3_5NM_UNI_QSERDES_RX_VTH_MAX_THRESH			0x1b8
> > +#define USB3_5NM_UNI_QSERDES_RX_ALOG_OBSV_BUS_CTRL_1		0x1bc
> > +#define USB3_5NM_UNI_QSERDES_RX_PI_CTRL1			0x1c0
> > +#define USB3_5NM_UNI_QSERDES_RX_PI_CTRL2			0x1c4
> > +#define USB3_5NM_UNI_QSERDES_RX_PI_QUAD				0x1c8
> > +#define USB3_5NM_UNI_QSERDES_RX_IDATA1				0x1cc
> > +#define USB3_5NM_UNI_QSERDES_RX_IDATA2				0x1d0
> > +#define USB3_5NM_UNI_QSERDES_RX_AUX_DATA1			0x1d4
> > +#define USB3_5NM_UNI_QSERDES_RX_AUX_DATA2			0x1d8
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_OUTP			0x1dc
> > +#define USB3_5NM_UNI_QSERDES_RX_AC_JTAG_OUTN			0x1e0
> > +#define USB3_5NM_UNI_QSERDES_RX_RX_SIGDET			0x1e4
> > +#define USB3_5NM_UNI_QSERDES_RX_ALOG_OBSV_BUS_STATUS_1		0x1e8
> > +
> > +/* Module:  USB3_UNI_PCS_LN_PCIE_USB3_UNI_PCS_LANE */
> > +#define USB3_5NM_UNI_PCS_LN_PCS_STATUS1				0x00
> > +#define USB3_5NM_UNI_PCS_LN_PCS_STATUS2				0x04
> > +#define USB3_5NM_UNI_PCS_LN_PCS_STATUS2_CLEAR			0x08
> > +#define USB3_5NM_UNI_PCS_LN_PCS_STATUS3				0x0c
> > +#define USB3_5NM_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS		0x10
> > +#define USB3_5NM_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS		0x14
> > +#define USB3_5NM_UNI_PCS_LN_BIST_CHK_STATUS			0x18
> > +#define USB3_5NM_UNI_PCS_LN_INSIG_SW_CTRL1			0x1c
> > +#define USB3_5NM_UNI_PCS_LN_INSIG_MX_CTRL1			0x20
> > +#define USB3_5NM_UNI_PCS_LN_OUTSIG_SW_CTRL1			0x24
> > +#define USB3_5NM_UNI_PCS_LN_OUTSIG_MX_CTRL1			0x28
> > +#define USB3_5NM_UNI_PCS_LN_TEST_CONTROL1			0x2c
> > +#define USB3_5NM_UNI_PCS_LN_BIST_CTRL				0x30
> > +#define USB3_5NM_UNI_PCS_LN_PRBS_SEED0				0x34
> > +#define USB3_5NM_UNI_PCS_LN_PRBS_SEED1				0x38
> > +#define USB3_5NM_UNI_PCS_LN_FIXED_PAT_CTRL			0x3c
> > +#define USB3_5NM_UNI_PCS_LN_EQ_CONFIG				0x40
> > +#define USB3_5NM_UNI_PCS_LN_TEST_CONTROL2			0x44
> > +#define USB3_5NM_UNI_PCS_LN_TEST_CONTROL3			0x48
> > +
> > +/* Module: USB3_UNI_PCS_PCIE_LN_PCIE_USB3_UNI_PCS_PCIE_LANE */
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST	0x00
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST_RS	0x04
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_EN		0x08
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_DSBL_L			0x0c
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_PRESET_DSBL_H			0x10
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_LANE_OFF_CONFIG		0x14
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG1		0x18
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG2		0x1c
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_PCIE_PCS_STATUS		0x20
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_INSIG_SW_CTRL2			0x24
> > +#define USB3_5NM_UNI_PCS_PCIE_LN_INSIG_MX_CTRL2			0x28
> > +
> > +/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS */
> > +#define USB3_5NM_UNI_PCS_SW_RESET				0x000
> > +#define USB3_5NM_UNI_PCS_REVISION_ID0				0x004
> > +#define USB3_5NM_UNI_PCS_REVISION_ID1				0x008
> > +#define USB3_5NM_UNI_PCS_REVISION_ID2				0x00c
> > +#define USB3_5NM_UNI_PCS_REVISION_ID3				0x010
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS1				0x014
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS2				0x018
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS3				0x01c
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS4				0x020
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS5				0x024
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS6				0x028
> > +#define USB3_5NM_UNI_PCS_PCS_STATUS7				0x02c
> > +#define USB3_5NM_UNI_PCS_DEBUG_BUS_0_STATUS			0x030
> > +#define USB3_5NM_UNI_PCS_DEBUG_BUS_1_STATUS			0x034
> > +#define USB3_5NM_UNI_PCS_DEBUG_BUS_2_STATUS			0x038
> > +#define USB3_5NM_UNI_PCS_DEBUG_BUS_3_STATUS			0x03c
> > +#define USB3_5NM_UNI_PCS_POWER_DOWN_CONTROL			0x040
> > +#define USB3_5NM_UNI_PCS_START_CONTROL				0x044
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL1				0x048
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL2				0x04c
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL3				0x050
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL4				0x054
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL5				0x058
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL6				0x05c
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL7				0x060
> > +#define USB3_5NM_UNI_PCS_INSIG_SW_CTRL8				0x064
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL1				0x068
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL2				0x06c
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL3				0x070
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL4				0x074
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL5				0x078
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL7				0x07c
> > +#define USB3_5NM_UNI_PCS_INSIG_MX_CTRL8				0x080
> > +#define USB3_5NM_UNI_PCS_OUTSIG_SW_CTRL1			0x084
> > +#define USB3_5NM_UNI_PCS_OUTSIG_MX_CTRL1			0x088
> > +#define USB3_5NM_UNI_PCS_CLAMP_ENABLE				0x08c
> > +#define USB3_5NM_UNI_PCS_POWER_STATE_CONFIG1			0x090
> > +#define USB3_5NM_UNI_PCS_POWER_STATE_CONFIG2			0x094
> > +#define USB3_5NM_UNI_PCS_FLL_CNTRL1				0x098
> > +#define USB3_5NM_UNI_PCS_FLL_CNTRL2				0x09c
> > +#define USB3_5NM_UNI_PCS_FLL_CNT_VAL_L				0x0a0
> > +#define USB3_5NM_UNI_PCS_FLL_CNT_VAL_H_TOL			0x0a4
> > +#define USB3_5NM_UNI_PCS_FLL_MAN_CODE				0x0a8
> > +#define USB3_5NM_UNI_PCS_TEST_CONTROL1				0x0ac
> > +#define USB3_5NM_UNI_PCS_TEST_CONTROL2				0x0b0
> > +#define USB3_5NM_UNI_PCS_TEST_CONTROL3				0x0b4
> > +#define USB3_5NM_UNI_PCS_TEST_CONTROL4				0x0b8
> > +#define USB3_5NM_UNI_PCS_TEST_CONTROL5				0x0bc
> > +#define USB3_5NM_UNI_PCS_TEST_CONTROL6				0x0c0
> > +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG1			0x0c4
> > +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG2			0x0c8
> > +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG3			0x0cc
> > +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG4			0x0d0
> > +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG5			0x0d4
> > +#define USB3_5NM_UNI_PCS_LOCK_DETECT_CONFIG6			0x0d8
> > +#define USB3_5NM_UNI_PCS_REFGEN_REQ_CONFIG1			0x0dc
> > +#define USB3_5NM_UNI_PCS_REFGEN_REQ_CONFIG2			0x0e0
> > +#define USB3_5NM_UNI_PCS_REFGEN_REQ_CONFIG3			0x0e4
> > +#define USB3_5NM_UNI_PCS_BIST_CTRL				0x0e8
> > +#define USB3_5NM_UNI_PCS_PRBS_POLY0				0x0ec
> > +#define USB3_5NM_UNI_PCS_PRBS_POLY1				0x0f0
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT0				0x0f4
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT1				0x0f8
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT2				0x0fc
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT3				0x100
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT4				0x104
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT5				0x108
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT6				0x10c
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT7				0x110
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT8				0x114
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT9				0x118
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT10				0x11c
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT11				0x120
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT12				0x124
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT13				0x128
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT14				0x12c
> > +#define USB3_5NM_UNI_PCS_FIXED_PAT15				0x130
> > +#define USB3_5NM_UNI_PCS_TXMGN_CONFIG				0x134
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V0				0x138
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V1				0x13c
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V2				0x140
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V3				0x144
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V4				0x148
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V0_RS			0x14c
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V1_RS			0x150
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V2_RS			0x154
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V3_RS			0x158
> > +#define USB3_5NM_UNI_PCS_G12S1_TXMGN_V4_RS			0x15c
> > +#define USB3_5NM_UNI_PCS_G3S2_TXMGN_MAIN			0x160
> > +#define USB3_5NM_UNI_PCS_G3S2_TXMGN_MAIN_RS			0x164
> > +#define USB3_5NM_UNI_PCS_G12S1_TXDEEMPH_M6DB			0x168
> > +#define USB3_5NM_UNI_PCS_G12S1_TXDEEMPH_M3P5DB			0x16c
> > +#define USB3_5NM_UNI_PCS_G3S2_PRE_GAIN				0x170
> > +#define USB3_5NM_UNI_PCS_G3S2_POST_GAIN				0x174
> > +#define USB3_5NM_UNI_PCS_G3S2_PRE_POST_OFFSET			0x178
> > +#define USB3_5NM_UNI_PCS_G3S2_PRE_GAIN_RS			0x17c
> > +#define USB3_5NM_UNI_PCS_G3S2_POST_GAIN_RS			0x180
> > +#define USB3_5NM_UNI_PCS_G3S2_PRE_POST_OFFSET_RS		0x184
> > +#define USB3_5NM_UNI_PCS_RX_SIGDET_LVL				0x188
> > +#define USB3_5NM_UNI_PCS_RX_SIGDET_DTCT_CNTRL			0x18c
> > +#define USB3_5NM_UNI_PCS_RCVR_DTCT_DLY_P1U2_L			0x190
> > +#define USB3_5NM_UNI_PCS_RCVR_DTCT_DLY_P1U2_H			0x194
> > +#define USB3_5NM_UNI_PCS_RATE_SLEW_CNTRL1			0x198
> > +#define USB3_5NM_UNI_PCS_RATE_SLEW_CNTRL2			0x19c
> > +#define USB3_5NM_UNI_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x1a0
> > +#define USB3_5NM_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L		0x1a4
> > +#define USB3_5NM_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H		0x1a8
> > +#define USB3_5NM_UNI_PCS_TSYNC_RSYNC_TIME			0x1ac
> > +#define USB3_5NM_UNI_PCS_CDR_RESET_TIME				0x1b0
> > +#define USB3_5NM_UNI_PCS_TSYNC_DLY_TIME				0x1b4
> > +#define USB3_5NM_UNI_PCS_ELECIDLE_DLY_SEL			0x1b8
> > +#define USB3_5NM_UNI_PCS_CMN_ACK_OUT_SEL			0x1bc
> > +#define USB3_5NM_UNI_PCS_ALIGN_DETECT_CONFIG1			0x1c0
> > +#define USB3_5NM_UNI_PCS_ALIGN_DETECT_CONFIG2			0x1c4
> > +#define USB3_5NM_UNI_PCS_ALIGN_DETECT_CONFIG3			0x1c8
> > +#define USB3_5NM_UNI_PCS_ALIGN_DETECT_CONFIG4			0x1cc
> > +#define USB3_5NM_UNI_PCS_PCS_TX_RX_CONFIG			0x1d0
> > +#define USB3_5NM_UNI_PCS_RX_IDLE_DTCT_CNTRL			0x1d4
> > +#define USB3_5NM_UNI_PCS_RX_DCC_CAL_CONFIG			0x1d8
> > +#define USB3_5NM_UNI_PCS_EQ_CONFIG1				0x1dc
> > +#define USB3_5NM_UNI_PCS_EQ_CONFIG2				0x1e0
> > +#define USB3_5NM_UNI_PCS_EQ_CONFIG3				0x1e4
> > +#define USB3_5NM_UNI_PCS_EQ_CONFIG4				0x1e8
> > +#define USB3_5NM_UNI_PCS_EQ_CONFIG5				0x1ec
> > +
> > +/* Module: USB3_UNI_PHY_PCIE_PCS */
> > +#define USB3_5NM_UNI_PCS_PCIE_INT_AUX_CLK_STATUS		0x00
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_STATUS			0x04
> > +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG1		0x08
> > +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG2		0x0c
> > +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG3		0x10
> > +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG4		0x14
> > +#define USB3_5NM_UNI_PCS_PCIE_POWER_STATE_CONFIG5		0x18
> > +#define USB3_5NM_UNI_PCS_PCIE_PCS_TX_RX_CONFIG			0x1c
> > +#define USB3_5NM_UNI_PCS_PCIE_ENDPOINT_REFCLK_DRIVE		0x20
> > +#define USB3_5NM_UNI_PCS_PCIE_ENDPOINT_REFCLK_CNTRL		0x24
> > +#define USB3_5NM_UNI_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK	0x28
> > +#define USB3_5NM_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L		0x2c
> > +#define USB3_5NM_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H		0x30
> > +#define USB3_5NM_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL1		0x34
> > +#define USB3_5NM_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL2		0x38
> > +#define USB3_5NM_UNI_PCS_PCIE_SIGDET_CNTRL			0x3c
> > +#define USB3_5NM_UNI_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME		0x40
> > +#define USB3_5NM_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L	0x44
> > +#define USB3_5NM_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H	0x48
> > +#define USB3_5NM_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L	0x4c
> > +#define USB3_5NM_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H	0x50
> > +#define USB3_5NM_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG1		0x54
> > +#define USB3_5NM_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG2		0x58
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG1			0x5c
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG2			0x60
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG3			0x64
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG4			0x68
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG5			0x6c
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG6			0x70
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_CONFIG7			0x74
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1		0x78
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2		0x7c
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3		0x80
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4		0x84
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5		0x88
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6		0x8c
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7		0x90
> > +#define USB3_5NM_UNI_PCS_PCIE_OSC_DTCT_ACTIONS			0x94
> > +#define USB3_5NM_UNI_PCS_PCIE_LOCAL_FS				0x98
> > +#define USB3_5NM_UNI_PCS_PCIE_LOCAL_LF				0x9c
> > +#define USB3_5NM_UNI_PCS_PCIE_LOCAL_FS_RS			0xa0
> > +#define USB3_5NM_UNI_PCS_PCIE_EQ_CONFIG1			0xa4
> > +#define USB3_5NM_UNI_PCS_PCIE_EQ_CONFIG2			0xa8
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P0_P1_PRE			0xac
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P2_P3_PRE			0xb0
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P4_P5_PRE			0xb4
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P6_P7_PRE			0xb8
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P8_P9_PRE			0xbc
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P10_PRE			0xc0
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P1_P3_PRE_RS		0xc4
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P4_P5_PRE_RS		0xc8
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P6_P9_PRE_RS		0xcc
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P0_P1_POST			0xd0
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P2_P3_POST			0xd4
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P4_P5_POST			0xd8
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P6_P7_POST			0xdc
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P8_P9_POST			0xe0
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P10_POST			0xe4
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P1_P3_POST_RS		0xe8
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P4_P5_POST_RS		0xec
> > +#define USB3_5NM_UNI_PCS_PCIE_PRESET_P6_P9_POST_RS		0xf0
> > +#define USB3_5NM_UNI_PCS_PCIE_RXEQEVAL_TIME			0xf4
> > +
> > +/* Module: USB3_UNI_PHY_PCIE_PCS_DEBUG_INTGEN */
> > +#define USB3_5NM_UNI_PCS_INTGEN_INTGEN_STATUS1			0x00
> > +#define USB3_5NM_UNI_PCS_INTGEN_INTGEN_STATUS2			0x04
> > +#define USB3_5NM_UNI_PCS_INTGEN_CONFIG1				0x08
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG1		0x0c
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG2		0x10
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG3		0x14
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG4		0x18
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG5		0x1c
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG1		0x20
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG2		0x24
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG3		0x28
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG4		0x2c
> > +#define USB3_5NM_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG5		0x30
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG1		0x34
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG2		0x38
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG3		0x3c
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG4		0x40
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK1_CONFIG5		0x44
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG1		0x48
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG2		0x4c
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG3		0x50
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG4		0x54
> > +#define USB3_5NM_UNI_PCS_INTGEN_STRINGBLK2_CONFIG5		0x58
> > +
> > +
> > +/* Module: USB3_UNI_PCS_USB3_PCIE_USB3_UNI_PCS_USB3 */
> > +#define USB3_5NM_UNI_PCS_USB3_POWER_STATE_CONFIG1		0x00
> > +#define USB3_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS		0x04
> > +#define USB3_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL		0x08
> > +#define USB3_5NM_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL2		0x0c
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS	0x10
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR		0x14
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL		0x18
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_TX_ECSTART			0x1c
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_PER_TIMER_VAL		0x20
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_TX_END_CNT_U3_START		0x24
> > +#define USB3_5NM_UNI_PCS_USB3_LFPS_CONFIG1			0x28
> > +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_LOCK_TIME		0x2c
> > +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME		0x30
> > +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_CTLE_TIME		0x34
> > +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2		0x38
> > +#define USB3_5NM_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2		0x3c
> > +#define USB3_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L		0x40
> > +#define USB3_5NM_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H		0x44
> > +#define USB3_5NM_UNI_PCS_USB3_ARCVR_DTCT_EN_PERIOD		0x48
> > +#define USB3_5NM_UNI_PCS_USB3_ARCVR_DTCT_CM_DLY			0x4c
> > +#define USB3_5NM_UNI_PCS_USB3_TXONESZEROS_RUN_LENGTH		0x50
> > +#define USB3_5NM_UNI_PCS_USB3_ALFPS_DEGLITCH_VAL		0x54
> > +#define USB3_5NM_UNI_PCS_USB3_SIGDET_STARTUP_TIMER_VAL		0x58
> > +#define USB3_5NM_UNI_PCS_USB3_TEST_CONTROL			0x5c
> > +#define USB3_5NM_UNI_PCS_USB3_RXTERMINATION_DLY_SEL		0x60
> > +
> > +#endif
> > -- 
> > 2.35.1
> 
> -- 
> ~Vinod

On Tue 17 May 03:36 PDT 2022, Vinod Koul wrote:

> On 17-05-22, 16:01, Vinod Koul wrote:
> > On 13-05-22, 15:53, Bjorn Andersson wrote:
> > > Add all registers defines from qcom,usb3-5nm-qmp-uni.h of the msm-5.4
> > > kernel. Offsets are adjusted to be relative to each sub-block, as we
> > > describe the individual pieces in the upstream kernel and "5NM" are
> > > injected in the defines to not collide with existing constants.
> > > 
> > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > ---
> > >  .../phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h  | 617 ++++++++++++++++++
> > >  1 file changed, 617 insertions(+)
> > >  create mode 100644 drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> > > 
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> > > new file mode 100644
> > > index 000000000000..b912e50825f9
> > > --- /dev/null
> > > +++ b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> > > @@ -0,0 +1,617 @@
> > > +/* SPDX-License-Identifier: GPL-2.0-only */
> > > +/*
> > > + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> > 
> > should this be 2022 or add Linaro one for 2022..?
> > 
> > > + */
> > > +
> > > +#ifndef PHY_QCOM_USB3_5NM_QMP_UNI_H_
> > > +#define PHY_QCOM_USB3_5NM_QMP_UNI_H_
> > > +
> > > +/* Module: USB3_UNI_PHY_QSERDES_COM_QSERDES_COM_PCIE_USB3_UNI_QMP_PLL */
> > > +#define USB3_5NM_UNI_QSERDES_COM_ATB_SEL1			0x000
> > > +#define USB3_5NM_UNI_QSERDES_COM_ATB_SEL2			0x004
> > > +#define USB3_5NM_UNI_QSERDES_COM_FREQ_UPDATE			0x008
> > > +#define USB3_5NM_UNI_QSERDES_COM_BG_TIMER			0x00c
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_EN_CENTER			0x010
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_ADJ_PER1			0x014
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_ADJ_PER2			0x018
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_PER1			0x01c
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_PER2			0x020
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0		0x024
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0		0x028
> 
> this seems to be QSERDES_V3_COM_* uptill now...
> 

Yes, some of these will be the same across several different versions of
QMP phys.

It takes me quite a bit of time trying to puzzle in missing entries in
the right place in the existing sets of defines. So the proposal here is
to use the generated files that exists for many of the QMP variants
downstream.

An example of this is that I got the USB combo phy for sc8280xp wrong,
because I couldn't copy paste the initialization sequence from the
downstream dts and we have mangled the names in the header file. So
either we just use the generated downstream file, or I will have to
spend a bunch of time trying to figure out which register(s) I got
wrong.

> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE0		0x02c
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1		0x030
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1		0x034
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE1		0x038
> > > +#define USB3_5NM_UNI_QSERDES_COM_POST_DIV			0x03c
> > > +#define USB3_5NM_UNI_QSERDES_COM_POST_DIV_MUX			0x040
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIAS_EN_CLKBUFLR_EN		0x044
> > > +#define USB3_5NM_UNI_QSERDES_COM_CLK_ENABLE1			0x048
> > > +#define USB3_5NM_UNI_QSERDES_COM_SYS_CLK_CTRL			0x04c
> > > +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE		0x050
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_EN				0x054
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_IVCO			0x058
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_IETRIM			0x05c
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_IPTRIM			0x060
> > > +#define USB3_5NM_UNI_QSERDES_COM_EP_CLOCK_DETECT_CTRL		0x064
> > > +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_DET_COMP_STATUS		0x068
> > > +#define USB3_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE0		0x06c
> > > +#define USB3_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE1		0x070
> > > +#define USB3_5NM_UNI_QSERDES_COM_CP_CTRL_MODE0			0x074
> > > +#define USB3_5NM_UNI_QSERDES_COM_CP_CTRL_MODE1			0x078
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE0		0x07c
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE1		0x080
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE0		0x084
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE1		0x088
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_CNTRL			0x08c
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIAS_EN_CTRL_BY_PSM		0x090
> > > +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_EN_SEL			0x094
> > > +#define USB3_5NM_UNI_QSERDES_COM_CML_SYSCLK_SEL			0x098
> > > +#define USB3_5NM_UNI_QSERDES_COM_RESETSM_CNTRL			0x09c
> > > +#define USB3_5NM_UNI_QSERDES_COM_RESETSM_CNTRL2			0x0a0
> > > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP_EN			0x0a4
> > > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP_CFG			0x0a8
> > > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE0		0x0ac
> > > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE0		0x0b0
> > > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE1		0x0b4
> > > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE1		0x0b8
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MODE0		0x0bc
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE0		0x0c0
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MODE1		0x0c4
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE1		0x0c8
> > > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0		0x0cc
> > > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0		0x0d0
> > > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0		0x0d4
> > > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1		0x0d8
> > > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1		0x0dc
> > > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1		0x0e0
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_INITVAL		0x0e4
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_EN			0x0e8
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE0		0x0ec
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE0		0x0f0
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE1		0x0f4
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE1		0x0f8
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0		0x0fc
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1		0x100
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCOCAL_DEADMAN_CTRL		0x104
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_CTRL			0x108
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAP			0x10c
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE0		0x110
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE0		0x114
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE1		0x118
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE1		0x11c
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL1		0x120
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL2		0x124
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL1		0x128
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL2		0x12c
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL1		0x130
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL2		0x134
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER1		0x138
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER2		0x13c
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_STATUS			0x140
> > > +#define USB3_5NM_UNI_QSERDES_COM_RESET_SM_STATUS		0x144
> > > +#define USB3_5NM_UNI_QSERDES_COM_RESTRIM_CODE_STATUS		0x148
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLLCAL_CODE1_STATUS		0x14c
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLLCAL_CODE2_STATUS		0x150
> > > +#define USB3_5NM_UNI_QSERDES_COM_CLK_SELECT			0x154
> > > +#define USB3_5NM_UNI_QSERDES_COM_HSCLK_SEL			0x158
> > > +#define USB3_5NM_UNI_QSERDES_COM_HSCLK_HS_SWITCH_SEL		0x15c
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_BINCODE_STATUS	0x160
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_ANALOG			0x164
> > > +#define USB3_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE0		0x168
> > > +#define USB3_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE1		0x16c
> > > +#define USB3_5NM_UNI_QSERDES_COM_SW_RESET			0x170
> > > +#define USB3_5NM_UNI_QSERDES_COM_CORE_CLK_EN			0x174
> > > +#define USB3_5NM_UNI_QSERDES_COM_C_READY_STATUS			0x178
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_CONFIG			0x17c
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_RATE_OVERRIDE		0x180
> > > +#define USB3_5NM_UNI_QSERDES_COM_SVS_MODE_CLK_SEL		0x184
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS0			0x188
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS1			0x18c
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS2			0x190
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS3			0x194
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS_SEL			0x198
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_MISC1			0x19c
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_MODE			0x1a0
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_MODE_CONTD			0x1a4
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_DC_LEVEL_CTRL		0x1a8
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0x1ac
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1b0
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0x1b4
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1b8
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL		0x1bc
> > > +#define USB3_5NM_UNI_QSERDES_COM_RESERVED_1			0x1c0
> > > +#define USB3_5NM_UNI_QSERDES_COM_MODE_OPERATION_STATUS		0x1c4
> 
> these are offset now...
> 

Not sure I see what you mean?

> Any reason why this should be 5NM and not use the VX convention we
> have...?
> 

The downstream file is named "5nm" and not V5, so this was simply an
attempt to reduce the effort spent maintaining these defines.

Regards,
Bjorn