@@ -31,13 +31,7 @@ config SOC_IMX51
select ARCH_MXC_AUDMUX_V2
select ARCH_HAS_CPUFREQ
select ARCH_MX51
- select GENERIC_CLK
- select GENERIC_CLK_FIXED
- select GENERIC_CLK_DIVIDER
- select GENERIC_CLK_MUX
- select GENERIC_CLK_DUMMY
- select IMX_CLK_PLLV2
- select IMX_CLK_GATE2B
+ select IMX51_IMX53_CLK
config SOC_IMX53
bool
@@ -46,13 +40,7 @@ config SOC_IMX53
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MX53
- select GENERIC_CLK
- select GENERIC_CLK_FIXED
- select GENERIC_CLK_DIVIDER
- select GENERIC_CLK_MUX
- select GENERIC_CLK_DUMMY
- select IMX_CLK_PLLV2
- select IMX_CLK_GATE2B
+ select IMX51_IMX53_CLK
#comment "i.MX50 machines:"
@@ -3,7 +3,7 @@
#
# Object file lists.
-obj-y := cpu.o mm.o clock-imx51-imx53.o ehci.o system.o
+obj-y := cpu.o mm.o ehci.o system.o
obj-$(CONFIG_PM) += pm-imx5.o
obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
@@ -27,12 +27,12 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx53.h>
+#include <mach/crm_mx51_mx53_regs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include "crm_regs.h"
#include "devices-imx53.h"
#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31)
@@ -27,6 +27,7 @@
#include <linux/spi/spi.h>
#include <mach/common.h>
#include <mach/hardware.h>
+#include <mach/crm_mx51_mx53_regs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
@@ -37,7 +38,6 @@
#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
#define MX53EVK_LED IMX_GPIO_NR(7, 7)
-#include "crm_regs.h"
#include "devices-imx53.h"
static iomux_v3_cfg_t mx53_evk_pads[] = {
@@ -27,12 +27,12 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx53.h>
+#include <mach/crm_mx51_mx53_regs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include "crm_regs.h"
#include "devices-imx53.h"
#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8)
@@ -26,12 +26,12 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx53.h>
+#include <mach/crm_mx51_mx53_regs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include "crm_regs.h"
#include "devices-imx53.h"
#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
deleted file mode 100644
@@ -1,640 +0,0 @@
-/*
- * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <asm/div64.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/clock.h>
-
-#include "crm_regs.h"
-
-struct clk_dummy {
- struct clk clk;
-};
-
-static struct clk_hw_ops dumy_ops;
-static struct clk_dummy dummy = {
- .clk = {
- .name = "dummy",
- .ops = &dumy_ops,
- },
-};
-
-static DEFINE_CLK_FIXED(ckil, 0);
-static DEFINE_CLK_FIXED(osc, 0);
-static DEFINE_CLK_FIXED(ckih1, 0);
-static DEFINE_CLK_FIXED(ckih2, 0);
-
-static DEFINE_CLK_PLLV2(pll1, &osc.clk, MX51_DPLL1_BASE);
-static DEFINE_CLK_PLLV2(pll2, &osc.clk, MX51_DPLL2_BASE);
-static DEFINE_CLK_PLLV2(pll3, &osc.clk, MX51_DPLL3_BASE);
-static DEFINE_CLK_PLLV2(pll4, &osc.clk, MX53_DPLL4_BASE);
-
-static struct clk_dummy dummy;
-
-/* Low-power Audio Playback Mode clock */
-static struct clk *lp_apm_sel[] = {
- &osc.clk,
- NULL,
-};
-static IMX_DEFINE_CLK_MUX(lp_apm, MXC_CCM_CCSR, 9, 1, lp_apm_sel);
-
-static IMX_DEFINE_CLK_DIVIDER(step_pll2_div, &pll2.clk, 0, MXC_CCM_CCSR, 5, 2);
-
-static IMX_DEFINE_CLK_DIVIDER(step_pll3_div, &pll3.clk, 0, MXC_CCM_CCSR, 3, 2);
-
-static struct clk *step_clk_sel[] = {
- &lp_apm.clk,
- NULL,
- &step_pll2_div.clk,
- &step_pll3_div.clk,
-};
-static IMX_DEFINE_CLK_MUX(step_clk, MXC_CCM_CCSR, 7, 2, step_clk_sel);
-
-static struct clk *pll1_sw_sel[] = {
- &pll1.clk,
- &step_clk.clk,
-};
-static IMX_DEFINE_CLK_MUX(pll1_sw, MXC_CCM_CCSR, 2, 1, pll1_sw_sel);
-
-static struct clk *pll2_sw_sel[] = {
- &pll2.clk,
- NULL,
-};
-static IMX_DEFINE_CLK_MUX(pll2_sw, MXC_CCM_CCSR, 1, 1, pll2_sw_sel);
-
-static struct clk *pll3_sw_sel[] = {
- &pll3.clk,
- NULL,
-};
-static IMX_DEFINE_CLK_MUX(pll3_sw, MXC_CCM_CCSR, 0, 1, pll3_sw_sel);
-
-static struct clk *pll4_sw_sel[] = {
- &pll4.clk,
- NULL,
-};
-static IMX_DEFINE_CLK_MUX(pll4_sw, MXC_CCM_CCSR, 9, 1, pll4_sw_sel);
-
-
-/* This is used multiple times */
-static struct clk *standard_pll_sel_clks[] = {
- &pll1_sw.clk,
- &pll2_sw.clk,
- &pll3_sw.clk,
- &lp_apm.clk,
-};
-
-static struct clk *periph_apm_sel[] = {
- &pll1_sw.clk,
- &pll3_sw.clk,
- &lp_apm.clk,
-};
-static IMX_DEFINE_CLK_MUX(periph_apm, MXC_CCM_CBCMR, 12, 2, periph_apm_sel);
-
-static struct clk *main_bus_sel[] = {
- &pll2_sw.clk,
- &periph_apm.clk,
-};
-static IMX_DEFINE_CLK_MUX(main_bus, MXC_CCM_CBCDR, 25, 1, main_bus_sel);
-
-static IMX_DEFINE_CLK_DIVIDER(ahb_root, &main_bus.clk, 0, MXC_CCM_CBCDR, 10, 3);
-static IMX_DEFINE_CLK_DIVIDER(ipg, &ahb_root.clk, 0, MXC_CCM_CBCDR, 8, 2);
-
-static struct clk *perclk_lp_apm_sel[] = {
- &main_bus.clk,
- &lp_apm.clk,
-};
-static IMX_DEFINE_CLK_MUX(perclk_lp_apm, MXC_CCM_CBCMR, 1, 1, perclk_lp_apm_sel);
-
-static IMX_DEFINE_CLK_DIVIDER(perclk_pred1, &perclk_lp_apm.clk, 0, MXC_CCM_CBCDR, 6, 2);
-static IMX_DEFINE_CLK_DIVIDER(perclk_pred2, &perclk_pred1.clk, 0, MXC_CCM_CBCDR, 3, 3);
-static IMX_DEFINE_CLK_DIVIDER(perclk_podf, &perclk_pred2.clk, CLK_PARENT_SET_RATE, MXC_CCM_CBCDR, 0, 3);
-
-static struct clk *ipg_perclk_sel[] = {
- &perclk_podf.clk,
- &ipg.clk,
-};
-static IMX_DEFINE_CLK_MUX(ipg_perclk, MXC_CCM_CBCMR, 0, 1, ipg_perclk_sel);
-
-static IMX_DEFINE_CLK_DIVIDER(axi_a, &main_bus.clk, 0, MXC_CCM_CBCDR, 16, 3);
-static IMX_DEFINE_CLK_DIVIDER(axi_b, &main_bus.clk, 0, MXC_CCM_CBCDR, 19, 3);
-
-static struct clk *emi_slow_sel_clks[] = {
- &main_bus.clk,
- &ahb_root.clk,
-};
-static IMX_DEFINE_CLK_MUX(emi_sel, MXC_CCM_CBCDR, 26, 1, emi_slow_sel_clks);
-static IMX_DEFINE_CLK_DIVIDER(emi_slow_podf, &emi_sel.clk, 0, MXC_CCM_CBCDR, 22, 3);
-static IMX_DEFINE_CLK_DIVIDER(nfc_podf, &emi_slow_podf.clk, 0, MXC_CCM_CBCDR, 13, 3);
-
-static struct clk *xpu_sel[] = {
- &axi_a.clk,
- &axi_b.clk,
- &emi_slow_podf.clk,
- &ahb_root.clk,
-};
-static IMX_DEFINE_CLK_MUX(gpu2d, MXC_CCM_CBCMR, 16, 2, xpu_sel);
-static IMX_DEFINE_CLK_MUX(arm_axi, MXC_CCM_CBCMR, 8, 2, xpu_sel);
-static IMX_DEFINE_CLK_MUX(ipu_hsp, MXC_CCM_CBCMR, 6, 2, xpu_sel);
-static IMX_DEFINE_CLK_MUX(gpu, MXC_CCM_CBCMR, 4, 2, xpu_sel);
-static IMX_DEFINE_CLK_MUX(vpu_axi_root, MXC_CCM_CBCMR, 14, 2, xpu_sel);
-static IMX_DEFINE_CLK_MUX(ddr_root, MXC_CCM_CBCMR, 10, 2, xpu_sel);
-
-static IMX_DEFINE_CLK_DIVIDER(ddr_hf_mx51, &pll1_sw.clk, 0, MXC_CCM_CBCDR, 27, 3);
-static struct clk *ddr_hf_sel[] = {
- &ddr_root.clk,
- &ddr_hf_mx51.clk,
-};
-static IMX_DEFINE_CLK_MUX(ddr_root_mx51, MXC_CCM_CBCDR, 30, 1, ddr_hf_sel);
-
-static IMX_DEFINE_CLK_MUX(uart_sel, MXC_CCM_CSCMR1, 24, 2, standard_pll_sel_clks);
-static IMX_DEFINE_CLK_DIVIDER(uart_pred, &uart_sel.clk, 0, MXC_CCM_CSCDR1, 3, 3);
-static IMX_DEFINE_CLK_DIVIDER(uart_root, &uart_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CSCDR1, 0, 3);
-
-static IMX_DEFINE_CLK_MUX(esdhc1_sel, MXC_CCM_CSCMR1, 20, 2, standard_pll_sel_clks);
-static IMX_DEFINE_CLK_DIVIDER(esdhc1_pred, &esdhc1_sel.clk, 0, MXC_CCM_CSCDR1, 16, 3);
-static IMX_DEFINE_CLK_DIVIDER(esdhc1_podf, &esdhc1_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CSCDR1, 11, 3);
-
-/* This is routed to esdhc3 in the i.MX53 datasheet */
-static IMX_DEFINE_CLK_MUX(esdhc2_sel, MXC_CCM_CSCMR1, 16, 2, standard_pll_sel_clks);
-static IMX_DEFINE_CLK_DIVIDER(esdhc2_pred, &esdhc2_sel.clk, 0, MXC_CCM_CSCDR1, 22, 3);
-static IMX_DEFINE_CLK_DIVIDER(esdhc2_podf, &esdhc2_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CSCDR1, 19, 3);
-
-static struct clk *esdhc3_sel_clks[] = {
- &esdhc1_podf.clk,
- &esdhc2_podf.clk,
-};
-static IMX_DEFINE_CLK_MUX(esdhc3_sel, MXC_CCM_CSCMR1, 19, 1, esdhc3_sel_clks);
-
-static struct clk *esdhc4_sel_clks[] = {
- &esdhc1_podf.clk,
- &esdhc2_podf.clk,
-};
-static IMX_DEFINE_CLK_MUX(esdhc4_sel, MXC_CCM_CSCMR1, 18, 1, esdhc4_sel_clks);
-
-static struct clk *ssi_apm_sel[] = {
- &ckih1.clk,
- &lp_apm.clk,
- &ckih2.clk,
-};
-static IMX_DEFINE_CLK_MUX(ssi_lp_apm, MXC_CCM_CSCMR1, 8, 2, ssi_apm_sel);
-static IMX_DEFINE_CLK_MUX(ssi1_clk_sel, MXC_CCM_CSCMR1, 14, 2, standard_pll_sel_clks);
-static IMX_DEFINE_CLK_DIVIDER(ssi1_clk_pred, &ssi1_clk_sel.clk, 0, MXC_CCM_CS1CDR, 6, 3);
-static IMX_DEFINE_CLK_DIVIDER(ssi1_clk, &ssi1_clk_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CS1CDR, 0, 6);
-static IMX_DEFINE_CLK_MUX(ssi2_clk_sel, MXC_CCM_CSCMR1, 12, 2, standard_pll_sel_clks);
-static IMX_DEFINE_CLK_DIVIDER(ssi2_clk_pred, &ssi2_clk_sel.clk, 0, MXC_CCM_CS2CDR, 6, 3);
-static IMX_DEFINE_CLK_DIVIDER(ssi2_clk, &ssi2_clk_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CS2CDR, 0, 6);
-static struct clk *ssi3_clk_sel[] = {
- &ssi1_clk.clk,
- &ssi2_clk.clk,
-};
-static IMX_DEFINE_CLK_MUX(ssi3_clk, MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sel);
-
-static IMX_DEFINE_CLK_MUX(ecspi_sel, MXC_CCM_CSCMR1, 4, 2, standard_pll_sel_clks);
-static IMX_DEFINE_CLK_DIVIDER(ecspi_pred, &ecspi_sel.clk, 0, MXC_CCM_CSCDR2, 25, 3);
-static IMX_DEFINE_CLK_DIVIDER(ecspi_podf, &ecspi_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CSCDR2, 19, 6);
-
-static IMX_DEFINE_CLK_MUX(usboh3_sel, MXC_CCM_CSCMR1, 22, 2, standard_pll_sel_clks);
-static IMX_DEFINE_CLK_DIVIDER(usboh3_pred, &usboh3_sel.clk, 0, MXC_CCM_CSCDR1, 8, 3);
-static IMX_DEFINE_CLK_DIVIDER(usboh3_podf, &usboh3_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CSCDR1, 6, 2);
-
-static IMX_DEFINE_CLK_DIVIDER(usb_phy_pred, &pll3_sw.clk, 0, MXC_CCM_CDCDR, 3, 3);
-static IMX_DEFINE_CLK_DIVIDER(usb_phy_podf, &usb_phy_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CDCDR, 0, 3);
-static struct clk *usb_phy_sel_clks[] = {
- &osc.clk,
- &usb_phy_podf.clk,
-};
-static IMX_DEFINE_CLK_MUX(usb_phy_sel, MXC_CCM_CSCMR1, 26, 1, usb_phy_sel_clks);
-
-static IMX_DEFINE_CLK_DIVIDER(cpu_podf, &pll1_sw.clk, 0, MXC_CCM_CACRR, 0, 3);
-
-static struct clk *ipu_di0_sel_clks[] = {
- &pll3_sw.clk,
- &osc.clk,
- &ckih1.clk,
- NULL, /* &tve_di.clk */
- NULL, /* ipp di0 (iomux) */
- NULL, /* ldp di0 */
-};
-static IMX_DEFINE_CLK_MUX(ipu_di0_sel, MXC_CCM_CSCMR2, 26, 3, ipu_di0_sel_clks);
-
-static struct clk *ipu_di1_sel_clks[] = {
- &pll3_sw.clk,
- &osc.clk,
- &ckih1.clk,
- NULL, /* &tve_di.clk */
- NULL, /* ipp di1 (iomux) */
- NULL, /* ldp di1 */
-};
-static IMX_DEFINE_CLK_MUX(ipu_di1_sel, MXC_CCM_CSCMR2, 29, 3, ipu_di1_sel_clks);
-
-static struct clk *tve_ext_sel_clks[] = {
- &osc.clk,
- &ckih1.clk,
-};
-static IMX_DEFINE_CLK_MUX(tve_ext_sel, MXC_CCM_CSCMR1, 6, 1, tve_ext_sel_clks);
-
-static IMX_DEFINE_CLK_DIVIDER(tve_pred, &pll3_sw.clk, 0, MXC_CCM_CDCDR, 28, 3);
-
-static struct clk *tve_sel_clks[] = {
- &tve_pred.clk,
- &tve_ext_sel.clk,
-};
-static IMX_DEFINE_CLK_MUX(tve_sel, MXC_CCM_CSCMR1, 7, 1, tve_sel_clks);
-
-static DEFINE_CLK_GATE2B(ahbmux1, &ipg.clk, MXC_CCM_CCGR0, 8);
-static DEFINE_CLK_GATE2B(aips_tz1, &ipg.clk, MXC_CCM_CCGR0, 12);
-static DEFINE_CLK_GATE2B(aips_tz2, &ipg.clk, MXC_CCM_CCGR0, 13);
-static DEFINE_CLK_GATE2B(ahb_max, &ipg.clk, MXC_CCM_CCGR0, 14);
-static DEFINE_CLK_GATE2B(iim_gate, &ipg.clk, MXC_CCM_CCGR0, 15);
-
-static DEFINE_CLK_GATE2B(uart1_ipg_gate, &ipg.clk, MXC_CCM_CCGR1, 3);
-static DEFINE_CLK_GATE2B(uart1_per_gate, &uart_root.clk, MXC_CCM_CCGR1, 4);
-static DEFINE_CLK_GATE2B(uart2_ipg_gate, &ipg.clk, MXC_CCM_CCGR1, 5);
-static DEFINE_CLK_GATE2B(uart2_per_gate, &uart_root.clk, MXC_CCM_CCGR1, 6);
-static DEFINE_CLK_GATE2B(uart3_ipg_gate, &ipg.clk, MXC_CCM_CCGR1, 7);
-static DEFINE_CLK_GATE2B(uart3_per_gate, &uart_root.clk, MXC_CCM_CCGR1, 8);
-static DEFINE_CLK_GATE2B(i2c1_gate, &ipg_perclk.clk, MXC_CCM_CCGR1, 9);
-static DEFINE_CLK_GATE2B(i2c2_gate, &ipg_perclk.clk, MXC_CCM_CCGR1, 10);
-static DEFINE_CLK_GATE2B(hsi2c_gate, &ipg.clk, MXC_CCM_CCGR1, 11);
-
-static DEFINE_CLK_GATE2B(mx51_usb_phy_gate, &usb_phy_sel.clk, MXC_CCM_CCGR2, 0);
-static DEFINE_CLK_GATE2B(gpt_ipg_gate, &ipg.clk, MXC_CCM_CCGR2, 10);
-static DEFINE_CLK_GATE2B(pwm1_ipg_gate, &ipg.clk, MXC_CCM_CCGR2, 5);
-static DEFINE_CLK_GATE2B(pwm1_hf_gate, &ipg_perclk.clk, MXC_CCM_CCGR2, 6);
-static DEFINE_CLK_GATE2B(pwm2_ipg_gate, &ipg.clk, MXC_CCM_CCGR2, 7);
-static DEFINE_CLK_GATE2B(pwm2_hf_gate, &ipg_perclk.clk, MXC_CCM_CCGR2, 8);
-static DEFINE_CLK_GATE2B(gpt_gate, &ipg.clk, MXC_CCM_CCGR2, 9);
-static DEFINE_CLK_GATE2B(fec_gate, &ipg.clk, MXC_CCM_CCGR2, 12);
-static DEFINE_CLK_GATE2B(usboh3_ahb_gate, &ipg.clk, MXC_CCM_CCGR2, 13);
-static DEFINE_CLK_GATE2B(usboh3_gate, &usboh3_podf.clk, MXC_CCM_CCGR2, 14);
-static DEFINE_CLK_GATE2B(tve_gate, &tve_sel.clk, MXC_CCM_CCGR2, 15);
-
-static DEFINE_CLK_GATE2B(esdhc1_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 0);
-static DEFINE_CLK_GATE2B(esdhc1_per_gate, &esdhc1_podf.clk, MXC_CCM_CCGR3, 1);
-static DEFINE_CLK_GATE2B(esdhc2_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 2);
-static DEFINE_CLK_GATE2B(esdhc2_per_gate, &esdhc2_podf.clk, MXC_CCM_CCGR3, 3);
-static DEFINE_CLK_GATE2B(esdhc3_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 4);
-static DEFINE_CLK_GATE2B(esdhc3_per_gate, &esdhc3_sel.clk, MXC_CCM_CCGR3, 5);
-static DEFINE_CLK_GATE2B(esdhc4_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 6);
-static DEFINE_CLK_GATE2B(esdhc4_per_gate, &esdhc4_sel.clk, MXC_CCM_CCGR3, 7);
-static DEFINE_CLK_GATE2B(ssi1_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 8);
-static DEFINE_CLK_GATE2B(ssi1_gate, &ssi1_clk.clk, MXC_CCM_CCGR3, 9);
-static DEFINE_CLK_GATE2B(ssi2_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 10);
-static DEFINE_CLK_GATE2B(ssi2_gate, &ssi2_clk.clk, MXC_CCM_CCGR3, 11);
-static DEFINE_CLK_GATE2B(ssi3_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 12);
-static DEFINE_CLK_GATE2B(ssi3_gate, &ssi3_clk.clk, MXC_CCM_CCGR3, 13);
-
-static DEFINE_CLK_GATE2B(mx51_mipi_hsc1_gate, &ipg.clk, MXC_CCM_CCGR4, 3);
-static DEFINE_CLK_GATE2B(mx51_mipi_hsc2_gate, &ipg.clk, MXC_CCM_CCGR4, 4);
-static DEFINE_CLK_GATE2B(mx51_mipi_esc_gate, &ipg.clk, MXC_CCM_CCGR4, 5);
-static DEFINE_CLK_GATE2B(mx51_mipi_hsp_gate, &ipg.clk, MXC_CCM_CCGR4, 6);
-
-static DEFINE_CLK_GATE2B(mx53_usb_phy1_gate, &usb_phy_sel.clk, MXC_CCM_CCGR4, 5);
-static DEFINE_CLK_GATE2B(mx53_usb_phy2_gate, &usb_phy_sel.clk, MXC_CCM_CCGR4, 6);
-static DEFINE_CLK_GATE2B(ecspi1_ipg_gate, &ipg.clk, MXC_CCM_CCGR4, 9);
-static DEFINE_CLK_GATE2B(ecspi1_per_gate, &ecspi_podf.clk, MXC_CCM_CCGR4, 10);
-static DEFINE_CLK_GATE2B(ecspi2_ipg_gate, &ipg.clk, MXC_CCM_CCGR4, 11);
-static DEFINE_CLK_GATE2B(ecspi2_per_gate, &ecspi_podf.clk, MXC_CCM_CCGR4, 12);
-static DEFINE_CLK_GATE2B(cspi_ipg_gate, &ipg.clk, MXC_CCM_CCGR4, 13);
-static DEFINE_CLK_GATE2B(sdma_gate, &ipg.clk, MXC_CCM_CCGR4, 15);
-
-static DEFINE_CLK_GATE2B(ipu_gate, &ipu_hsp.clk, MXC_CCM_CCGR5, 5);
-static DEFINE_CLK_GATE2B(emi_fast_gate, &dummy.clk, MXC_CCM_CCGR5, 7);
-static DEFINE_CLK_GATE2B(emi_slow_gate, &emi_slow_podf.clk, MXC_CCM_CCGR5, 8);
-static DEFINE_CLK_GATE2B(nfc_gate, &nfc_podf.clk, MXC_CCM_CCGR5, 10);
-
-static DEFINE_CLK_GATE2B(ipu_di0_gate, &ipu_di0_sel.clk, MXC_CCM_CCGR6, 5);
-static DEFINE_CLK_GATE2B(ipu_di1_gate, &ipu_di1_sel.clk, MXC_CCM_CCGR6, 6);
-
-#define _REGISTER_CLKDEV(d, n, c) \
- { \
- .dev_id = d, \
- .con_id = n, \
- .clk = c, \
- },
-
-static struct clk_lookup mx5_lookups[] = {
- _REGISTER_CLKDEV("imx21-uart.0", NULL, &uart1_per_gate.clk)
- _REGISTER_CLKDEV("imx21-uart.1", NULL, &uart2_per_gate.clk)
- _REGISTER_CLKDEV("imx21-uart.2", NULL, &uart3_per_gate.clk)
- _REGISTER_CLKDEV("mxc_pwm.0", "pwm", &pwm1_ipg_gate.clk)
- _REGISTER_CLKDEV("mxc_pwm.1", "pwm", &pwm2_ipg_gate.clk)
- _REGISTER_CLKDEV("imx-i2c.0", NULL, &i2c1_gate.clk)
- _REGISTER_CLKDEV("imx-i2c.1", NULL, &i2c2_gate.clk)
- _REGISTER_CLKDEV("mxc-ehci.0", "usb", &usboh3_gate.clk)
- _REGISTER_CLKDEV("mxc-ehci.0", "usb_ahb", &usboh3_ahb_gate.clk)
- _REGISTER_CLKDEV("mxc-ehci.0", "usb_phy1", &mx53_usb_phy1_gate.clk)
- _REGISTER_CLKDEV("mxc-ehci.1", "usb", &usboh3_gate.clk)
- _REGISTER_CLKDEV("mxc-ehci.1", "usb_ahb", &usboh3_ahb_gate.clk)
- _REGISTER_CLKDEV("mxc-ehci.2", "usb", &usboh3_gate.clk)
- _REGISTER_CLKDEV("mxc-ehci.2", "usb_ahb", &usboh3_ahb_gate.clk)
- _REGISTER_CLKDEV("fsl-usb2-udc", "usb", &usboh3_gate.clk)
- _REGISTER_CLKDEV("fsl-usb2-udc", "usb_ahb", &usboh3_ahb_gate.clk)
- _REGISTER_CLKDEV("mxc_nand", NULL, &nfc_gate.clk)
- _REGISTER_CLKDEV("imx-ssi.0", NULL, &ssi1_gate.clk)
- _REGISTER_CLKDEV("imx-ssi.1", NULL, &ssi2_gate.clk)
- _REGISTER_CLKDEV("imx-ssi.2", NULL, &ssi3_gate.clk)
- _REGISTER_CLKDEV("imx-sdma", NULL, &sdma_gate.clk)
- _REGISTER_CLKDEV("imx51-ecspi.0", NULL, &ecspi1_per_gate.clk)
- _REGISTER_CLKDEV("imx51-ecspi.1", NULL, &ecspi2_per_gate.clk)
- _REGISTER_CLKDEV("imx51-cspi.0", NULL, &cspi_ipg_gate.clk)
- _REGISTER_CLKDEV(NULL, "cpu", &cpu_podf.clk)
- _REGISTER_CLKDEV(NULL, "iim", &iim_gate.clk)
- _REGISTER_CLKDEV("sdhci-esdhc-imx.0", NULL, &esdhc1_per_gate.clk)
- _REGISTER_CLKDEV("sdhci-esdhc-imx.1", NULL, &esdhc2_per_gate.clk)
- _REGISTER_CLKDEV("sdhci-esdhc-imx.2", NULL, &esdhc3_per_gate.clk)
- _REGISTER_CLKDEV("sdhci-esdhc-imx.3", NULL, &esdhc4_per_gate.clk)
- _REGISTER_CLKDEV("imx-ipuv3", NULL, &ipu_gate.clk)
- _REGISTER_CLKDEV("imx-ipuv3", "di0", &ipu_di0_gate.clk)
- _REGISTER_CLKDEV("imx-ipuv3", "di1", &ipu_di1_gate.clk)
- _REGISTER_CLKDEV("imx2-wdt.0", NULL, &dummy.clk)
- _REGISTER_CLKDEV("imx2-wdt.1", NULL, &dummy.clk)
- _REGISTER_CLKDEV("imx-keypad", NULL, &dummy.clk)
-};
-
-static struct clk_lookup mx51_lookups[] = {
- _REGISTER_CLKDEV("imx-i2c.2", NULL, &hsi2c_gate.clk)
- _REGISTER_CLKDEV("imx27-fec.0", NULL, &fec_gate.clk)
- _REGISTER_CLKDEV(NULL, "mipi_hsp", &mx51_mipi_hsp_gate.clk)
-};
-
-static struct clk_lookup mx53_lookups[] = {
- _REGISTER_CLKDEV("imx25-fec.0", NULL, &fec_gate.clk)
-};
-
-struct clk *mx5_on_clocks[] = {
- &uart1_ipg_gate.clk,
- &uart2_ipg_gate.clk,
- &uart3_ipg_gate.clk,
- &gpt_ipg_gate.clk,
- &esdhc1_ipg_gate.clk,
- &esdhc2_ipg_gate.clk,
- &esdhc3_ipg_gate.clk,
- &esdhc4_ipg_gate.clk,
- &ecspi1_ipg_gate.clk,
- &ecspi2_ipg_gate.clk,
- &cspi_ipg_gate.clk,
-};
-
-/*
- * TODO: macro help limit the effect of clk api change.
- * May be removed finally.
- */
-#define _REGISTER_CLK(_clk, _ops, _flags) \
- &(_clk).clk,
-
-struct clk *mx5_clk_array[] = {
- _REGISTER_CLK(ckil, &clk_fixed_ops, CLK_IS_ROOT)
- _REGISTER_CLK(osc, &clk_fixed_ops, CLK_IS_ROOT)
- _REGISTER_CLK(ckih1, &clk_fixed_ops, CLK_IS_ROOT)
- _REGISTER_CLK(ckih2, &clk_fixed_ops, CLK_IS_ROOT)
- _REGISTER_CLK(pll1, &clk_pllv2_ops, 0)
- _REGISTER_CLK(pll2, &clk_pllv2_ops, 0)
- _REGISTER_CLK(pll3, &clk_pllv2_ops, 0)
- /*
- * pll4 is only used by mx53. we put it here because
- * tve_ext_sel use it early
- */
- _REGISTER_CLK(pll4, &clk_pllv2_ops, 0)
- _REGISTER_CLK(pll4_sw, &clk_mux_ops, 0)
- _REGISTER_CLK(dummy, &clk_dummy_ops, CLK_IS_ROOT)
- _REGISTER_CLK(lp_apm, &clk_mux_ops, 0)
- _REGISTER_CLK(step_pll2_div, &clk_divider_ops, 0)
- _REGISTER_CLK(step_pll3_div, &clk_divider_ops, 0)
- _REGISTER_CLK(step_clk, &clk_mux_ops, 0)
- _REGISTER_CLK(pll1_sw, &clk_mux_ops, 0)
- _REGISTER_CLK(pll2_sw, &clk_mux_ops, 0)
- _REGISTER_CLK(pll3_sw, &clk_mux_ops, 0)
- _REGISTER_CLK(periph_apm, &clk_mux_ops, 0)
- _REGISTER_CLK(main_bus, &clk_mux_ops, 0)
- _REGISTER_CLK(ahb_root, &clk_divider_ops, 0)
- _REGISTER_CLK(ipg, &clk_divider_ops, 0)
- _REGISTER_CLK(perclk_lp_apm, &clk_mux_ops, 0)
- _REGISTER_CLK(perclk_pred1, &clk_divider_ops, 0)
- _REGISTER_CLK(perclk_pred2, &clk_divider_ops, 0)
- _REGISTER_CLK(perclk_podf, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
- _REGISTER_CLK(ipg_perclk, &clk_mux_ops, 0)
- _REGISTER_CLK(axi_a, &clk_divider_ops, 0)
- _REGISTER_CLK(axi_b, &clk_divider_ops, 0)
- _REGISTER_CLK(gpu2d, &clk_mux_ops, 0)
- _REGISTER_CLK(arm_axi, &clk_mux_ops, 0)
- _REGISTER_CLK(ipu_hsp, &clk_mux_ops, 0)
- _REGISTER_CLK(gpu, &clk_mux_ops, 0)
- _REGISTER_CLK(vpu_axi_root, &clk_mux_ops, 0)
- _REGISTER_CLK(ddr_root, &clk_mux_ops, 0)
- _REGISTER_CLK(uart_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(uart_pred, &clk_divider_ops, 0)
- _REGISTER_CLK(uart_root, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
- _REGISTER_CLK(esdhc1_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(esdhc1_pred, &clk_divider_ops, 0)
- _REGISTER_CLK(esdhc1_podf, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
- _REGISTER_CLK(esdhc2_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(esdhc2_pred, &clk_divider_ops, 0)
- _REGISTER_CLK(esdhc2_podf, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
- _REGISTER_CLK(esdhc3_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(esdhc4_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(emi_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(emi_slow_podf, &clk_divider_ops, 0)
- _REGISTER_CLK(nfc_podf, &clk_divider_ops, 0)
- _REGISTER_CLK(ssi_lp_apm, &clk_mux_ops, 0)
- _REGISTER_CLK(ssi1_clk_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(ssi1_clk_pred, &clk_divider_ops, 0)
- _REGISTER_CLK(ssi1_clk, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
- _REGISTER_CLK(ssi2_clk_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(ssi2_clk_pred, &clk_divider_ops, 0)
- _REGISTER_CLK(ssi2_clk, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
- _REGISTER_CLK(ssi3_clk, &clk_mux_ops, 0)
- _REGISTER_CLK(ecspi_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(ecspi_pred, &clk_divider_ops, 0)
- _REGISTER_CLK(ecspi_podf, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
- _REGISTER_CLK(usboh3_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(usboh3_pred, &clk_divider_ops, 0)
- _REGISTER_CLK(usboh3_podf, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
- _REGISTER_CLK(usb_phy_pred, &clk_divider_ops, 0)
- _REGISTER_CLK(usb_phy_podf, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
- _REGISTER_CLK(usb_phy_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(cpu_podf, &clk_divider_ops, 0)
- _REGISTER_CLK(ipu_di0_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(ipu_di1_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(tve_ext_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(tve_pred, &clk_divider_ops, 0)
- _REGISTER_CLK(tve_sel, &clk_mux_ops, 0)
- _REGISTER_CLK(ahbmux1, &clk_gate2b_ops, 0)
- _REGISTER_CLK(aips_tz1, &clk_gate2b_ops, 0)
- _REGISTER_CLK(aips_tz2, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ahb_max, &clk_gate2b_ops, 0)
- _REGISTER_CLK(iim_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(uart1_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(uart1_per_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(uart2_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(uart2_per_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(uart3_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(uart3_per_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(i2c1_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(i2c2_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(gpt_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(pwm1_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(pwm1_hf_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(pwm2_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(pwm2_hf_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(gpt_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(fec_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(usboh3_ahb_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(usboh3_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(tve_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(esdhc1_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(esdhc1_per_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(esdhc2_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(esdhc2_per_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(esdhc3_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(esdhc3_per_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(esdhc4_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(esdhc4_per_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ssi1_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ssi1_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ssi2_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ssi2_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ssi3_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ssi3_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ecspi1_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ecspi1_per_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ecspi2_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ecspi2_per_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(cspi_ipg_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(sdma_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ipu_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(emi_fast_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(emi_slow_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(nfc_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ipu_di0_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(ipu_di1_gate, &clk_gate2b_ops, 0)
-};
-
-struct clk *mx51_clk_array[] = {
- _REGISTER_CLK(ddr_hf_mx51, &clk_divider_ops, 0)
- _REGISTER_CLK(ddr_root_mx51, &clk_mux_ops, 0)
- _REGISTER_CLK(hsi2c_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(mx51_usb_phy_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(mx51_mipi_hsc1_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(mx51_mipi_hsc2_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(mx51_mipi_esc_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(mx51_mipi_hsp_gate, &clk_gate2b_ops, 0)
-};
-
-struct clk *mx53_clk_array[] = {
- _REGISTER_CLK(mx53_usb_phy1_gate, &clk_gate2b_ops, 0)
- _REGISTER_CLK(mx53_usb_phy2_gate, &clk_gate2b_ops, 0)
-};
-
-static void clk_register_array(struct clk **clks, int num)
-{
- int i;
-
- for (i = 0; i < num; i++)
- clk_init(NULL, clks[i]);
-}
-
-static void clkdev_add_array(struct clk_lookup *lookup, int num)
-{
- int i;
-
- for (i = 0; i < num; i++)
- clkdev_add(&lookup[i]);
-}
-
-static void mx5_clocks_common_init(unsigned long rate_ckil, unsigned long rate_osc,
- unsigned long rate_ckih1, unsigned long rate_ckih2)
-{
- int i;
-
- ckil.fixed_rate = rate_ckil;
- osc.fixed_rate = rate_osc;
- ckih1.fixed_rate = rate_ckih1;
- ckih2.fixed_rate = rate_ckih2;
-
- clk_register_array(mx5_clk_array, ARRAY_SIZE(mx5_clk_array));
- clkdev_add_array(mx5_lookups, ARRAY_SIZE(mx5_lookups));
-
- /* Set SDHC parents to be PLL2 */
- clk_set_parent(&esdhc1_sel.clk, &pll2_sw.clk);
- clk_set_parent(&esdhc2_sel.clk, &pll2_sw.clk);
-
- /* keep device ipg clocks on until drivers handle it */
- for (i = 0; i < ARRAY_SIZE(mx5_on_clocks); i++) {
- clk_prepare(mx5_on_clocks[i]);
- clk_enable(mx5_on_clocks[i]);
- }
-}
-
-int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
- unsigned long rate_ckih1, unsigned long rate_ckih2)
-{
- /* Clock tree has i.MX51 layout. i.MX53 needs some fixups */
- pll1.base = MX53_DPLL1_BASE;
- pll2.base = MX53_DPLL2_BASE;
- pll3.base = MX53_DPLL3_BASE;
- esdhc3_per_gate.clk.parent = &esdhc2_podf.clk;
- esdhc2_per_gate.clk.parent = &esdhc3_sel.clk;
- tve_gate.clk.parent = &tve_pred.clk;
- tve_pred.clk.parent = &tve_ext_sel.clk;
- tve_ext_sel_clks[0] = &pll4_sw.clk;
- tve_ext_sel_clks[1] = &ckih1.clk;
-
- mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
- clk_register_array(mx53_clk_array, ARRAY_SIZE(mx53_clk_array));
- clkdev_add_array(mx53_lookups, ARRAY_SIZE(mx53_lookups));
-
- /* set SDHC root clock to 200MHZ*/
- clk_set_rate(&esdhc1_podf.clk, 200000000);
- clk_set_rate(&esdhc2_podf.clk, 200000000);
-
- /* System timer */
- mxc_timer_init(&gpt_gate.clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
- MX53_INT_GPT);
-
- clk_prepare(&iim_gate.clk);
- clk_enable(&iim_gate.clk);
- imx_print_silicon_rev("i.MX53", mx53_revision());
- clk_disable(&iim_gate.clk);
- clk_unprepare(&iim_gate.clk);
-
- return 0;
-}
-
-int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
- unsigned long rate_ckih1, unsigned long rate_ckih2)
-{
- mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
- clk_register_array(mx51_clk_array, ARRAY_SIZE(mx5_clk_array));
- clkdev_add_array(mx51_lookups, ARRAY_SIZE(mx51_lookups));
-
- /* set SDHC root clock to 166.25MHZ*/
- clk_set_rate(&esdhc1_podf.clk, 166250000);
- clk_set_rate(&esdhc2_podf.clk, 166250000);
-
- /* System timer */
- mxc_timer_init(&gpt_gate.clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
- MX51_INT_GPT);
-
- clk_prepare(&iim_gate.clk);
- clk_enable(&iim_gate.clk);
- imx_print_silicon_rev("i.MX51", mx51_revision());
- clk_disable(&iim_gate.clk);
-
- return 0;
-}
deleted file mode 100644
@@ -1,600 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-
-#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
-#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
-#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
-#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
-#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
-#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
-
-/*MX53*/
-#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
-#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
-#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
-#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
-#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
-
-/* PLL Register Offsets */
-#define MXC_PLL_DP_CTL 0x00
-#define MXC_PLL_DP_CONFIG 0x04
-#define MXC_PLL_DP_OP 0x08
-#define MXC_PLL_DP_MFD 0x0C
-#define MXC_PLL_DP_MFN 0x10
-#define MXC_PLL_DP_MFNMINUS 0x14
-#define MXC_PLL_DP_MFNPLUS 0x18
-#define MXC_PLL_DP_HFS_OP 0x1C
-#define MXC_PLL_DP_HFS_MFD 0x20
-#define MXC_PLL_DP_HFS_MFN 0x24
-#define MXC_PLL_DP_MFN_TOGC 0x28
-#define MXC_PLL_DP_DESTAT 0x2c
-
-/* PLL Register Bit definitions */
-#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
-#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
-#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
-#define MXC_PLL_DP_CTL_ADE 0x800
-#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
-#define MXC_PLL_DP_CTL_HFSM 0x80
-#define MXC_PLL_DP_CTL_PRE 0x40
-#define MXC_PLL_DP_CTL_UPEN 0x20
-#define MXC_PLL_DP_CTL_RST 0x10
-#define MXC_PLL_DP_CTL_RCP 0x8
-#define MXC_PLL_DP_CTL_PLM 0x4
-#define MXC_PLL_DP_CTL_BRM0 0x2
-#define MXC_PLL_DP_CTL_LRF 0x1
-
-#define MXC_PLL_DP_CONFIG_BIST 0x8
-#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
-#define MXC_PLL_DP_CONFIG_AREN 0x2
-#define MXC_PLL_DP_CONFIG_LDREQ 0x1
-
-#define MXC_PLL_DP_OP_MFI_OFFSET 4
-#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
-#define MXC_PLL_DP_OP_PDF_OFFSET 0
-#define MXC_PLL_DP_OP_PDF_MASK 0xF
-
-#define MXC_PLL_DP_MFD_OFFSET 0
-#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_OFFSET 0x0
-#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
-#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
-#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
-#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
-
-#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
-#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
-
-/* Register addresses of CCM*/
-#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00)
-#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04)
-#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08)
-#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C)
-#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10)
-#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14)
-#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18)
-#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C)
-#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20)
-#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24)
-#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28)
-#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C)
-#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30)
-#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34)
-#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38)
-#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C)
-#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40)
-#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44)
-#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48)
-#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C)
-#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50)
-#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54)
-#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58)
-#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C)
-#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60)
-#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64)
-#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68)
-#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C)
-#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70)
-#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74)
-#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
-#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
-#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
-#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84)
-
-#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
-
-/* Define the bits in register CCR */
-#define MXC_CCM_CCR_COSC_EN (1 << 12)
-#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
-#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
-#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
-#define MXC_CCM_CCR_FPM_EN (1 << 8)
-#define MXC_CCM_CCR_OSCNT_OFFSET (0)
-#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
-
-/* Define the bits in register CCDR */
-#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
-#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
-#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
-
-/* Define the bits in register CSR */
-#define MXC_CCM_CSR_COSR_READY (1 << 5)
-#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
-#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
-#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
-#define MXC_CCM_CSR_FPM_READY (1 << 1)
-#define MXC_CCM_CSR_REF_EN_B (1 << 0)
-
-/* Define the bits in register CCSR */
-#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
-#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
-#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
-#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0
-#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */
-#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
-#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
-#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
-#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
-#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
-#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
-#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk,
- 1: step_clk */
-#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
-#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
-
-/* Define the bits in register CACRR */
-#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
-#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
-
-/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
-#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
-#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
-#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
-#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
-#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
-#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
-#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
-#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
-#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
-#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
-#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
-#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
-#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
-#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
-#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
-
-/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
-
-/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
-#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
-#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
-#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
-#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
-#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
-#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
-
-/* Define the bits in register CSCMR2 */
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
-#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
-#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
-#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
-#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
-#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
-#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
-#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
-#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
-
-/* Define the bits in register CSCDR1 */
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
-
-/* Define the bits in register CS1CDR and CS2CDR */
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
-
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
-
-/* Define the bits in register CDCDR */
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
-
-/* Define the bits in register CHSCCDR */
-#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
-
-/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
-
-/* Define the bits in register CSCDR3 */
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
-
-/* Define the bits in register CSCDR4 */
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
-
-/* Define the bits in register CDHIPR */
-#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
-#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
-#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
-#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
-#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
-#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
-#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
-#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
-#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
-#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
-
-/* Define the bits in register CDCR */
-#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
-
-/* Define the bits in register CLPCR */
-#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
-#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
-#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
-#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
-#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
-#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
-#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
-#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
-#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
-#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
-#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
-#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
-#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
-#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
-#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
-#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
-#define MXC_CCM_CLPCR_LPM_OFFSET (0)
-#define MXC_CCM_CLPCR_LPM_MASK (0x3)
-
-/* Define the bits in register CISR */
-#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
-#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
-#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
-#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
-#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
-#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
-#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
-#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
-#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
-#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
-#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
-#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
-#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
-#define MXC_CCM_CISR_LRF_PLL1 (0x1)
-
-/* Define the bits in register CIMR */
-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
-#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
-#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
-#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
-#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
-#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
-#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
-#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
-#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
-#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
-#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
-#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
-#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
-
-/* Define the bits in register CCOSR */
-#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
-#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
-#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
-#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
-#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
-#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
-#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
-#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
-#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
-#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
-
-/* Define the bits in registers CGPR */
-#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
-#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
-
-/* Define the bits in registers CCGRx */
-#define MXC_CCM_CCGRx_CG_MASK 0x3
-#define MXC_CCM_CCGRx_MOD_OFF 0x0
-#define MXC_CCM_CCGRx_MOD_ON 0x3
-#define MXC_CCM_CCGRx_MOD_IDLE 0x1
-
-#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30)
-#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10)
-#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8)
-#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6)
-#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2)
-#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0)
-
-#define MXC_CCM_CCGRx_CG15_OFFSET 30
-#define MXC_CCM_CCGRx_CG14_OFFSET 28
-#define MXC_CCM_CCGRx_CG13_OFFSET 26
-#define MXC_CCM_CCGRx_CG12_OFFSET 24
-#define MXC_CCM_CCGRx_CG11_OFFSET 22
-#define MXC_CCM_CCGRx_CG10_OFFSET 20
-#define MXC_CCM_CCGRx_CG9_OFFSET 18
-#define MXC_CCM_CCGRx_CG8_OFFSET 16
-#define MXC_CCM_CCGRx_CG7_OFFSET 14
-#define MXC_CCM_CCGRx_CG6_OFFSET 12
-#define MXC_CCM_CCGRx_CG5_OFFSET 10
-#define MXC_CCM_CCGRx_CG4_OFFSET 8
-#define MXC_CCM_CCGRx_CG3_OFFSET 6
-#define MXC_CCM_CCGRx_CG2_OFFSET 4
-#define MXC_CCM_CCGRx_CG1_OFFSET 2
-#define MXC_CCM_CCGRx_CG0_OFFSET 0
-
-#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
-#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
-#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
-#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
-#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
-#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
-#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
-#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
-#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
-#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
-#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
-#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
-#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
-
-/* CORTEXA8 platform */
-#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
-#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
-#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
-#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
-#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
-#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
-#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
-#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
-#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
-
-/* DVFS CORE */
-#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
-#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
-#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
-#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
-#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
-#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
-#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
-#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
-#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
-#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
-#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
-#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
-#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
-#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
-#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
-#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
-#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
-
-/* GPC */
-#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
-#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
-#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
-#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
-#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)
-#define MXC_GPC_PGR_ARMPG_OFFSET 8
-#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
-
-/* PGC */
-#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
-#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
-#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
-#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
-#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
-#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
-
-#define MXC_PGCR_PCR 1
-#define MXC_SRPGCR_PCR 1
-#define MXC_EMPGCR_PCR 1
-#define MXC_PGSR_PSR 1
-
-
-#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
-#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
-
-/* SRPG */
-#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
-#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
-#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
-
-#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
-#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
-#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
-#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
-#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
-#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
-#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
-
-#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
-#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
-#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
-
-#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
-#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
-#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
-
-#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
@@ -16,7 +16,7 @@
#include <asm/tlbflush.h>
#include <mach/common.h>
#include <mach/hardware.h>
-#include "crm_regs.h"
+#include <mach/crm_mx51_mx53_regs.h>
static struct clk *gpc_dvfs_clk;
@@ -14,7 +14,7 @@
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/common.h>
-#include "crm_regs.h"
+#include <mach/crm_mx51_mx53_regs.h>
/* set cpu low power mode before WFI instruction. This function is called
* mx5 because it can be used for mx50, mx51, and mx53.*/
@@ -6,8 +6,6 @@
obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
obj-$(CONFIG_ARM_GIC) += gic.o
-obj-$(CONFIG_IMX_CLK_PLLV2) += clk-pllv2.o
-obj-$(CONFIG_IMX_CLK_GATE2B) += clk-gate2b.o
obj-$(CONFIG_MXC_TZIC) += tzic.o
obj-$(CONFIG_MXC_AVIC) += avic.o
deleted file mode 100644
@@ -1,88 +0,0 @@
-/*
- * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <mach/clock.h>
-
-#define to_clk_gate2b(ck) container_of(ck, struct clk_gate2b, clk)
-
-static int clk_gate2b_enable(struct clk *clk)
-{
- struct clk_gate2b *gate2b = to_clk_gate2b(clk);
- unsigned long flags;
- u32 reg;
-
- if (gate2b->lock)
- spin_lock_irqsave(gate2b->lock, flags);
-
- reg = __raw_readl(gate2b->reg);
- reg &= ~(0x3 << gate2b->shift);
- reg |= gate2b->val_en << gate2b->shift;
- __raw_writel(reg, gate2b->reg);
-
- if (gate2b->lock)
- spin_unlock_irqrestore(gate2b->lock, flags);
-
- return 0;
-}
-
-static void clk_gate2b_disable(struct clk *clk)
-{
- struct clk_gate2b *gate2b = to_clk_gate2b(clk);
- unsigned long flags;
- u32 reg;
-
- if (gate2b->lock)
- spin_lock_irqsave(gate2b->lock, flags);
-
- reg = __raw_readl(gate2b->reg);
- reg &= ~(0x3 << gate2b->shift);
- reg |= gate2b->val_dis << gate2b->shift;
- __raw_writel(reg, gate2b->reg);
-
- if (gate2b->lock)
- spin_unlock_irqrestore(gate2b->lock, flags);
-
-}
-
-struct clk_hw_ops clk_gate2b_ops = {
- .enable = clk_gate2b_enable,
- .disable = clk_gate2b_disable,
-};
-EXPORT_SYMBOL_GPL(clk_gate2b_ops);
-
-int clk_gate2b_set_val(struct clk *clk, int en, int dis)
-{
- struct clk_gate2b *gate2b = to_clk_gate2b(clk);
- unsigned long flags;
- u32 reg, val;
-
- en &= 0x3;
- dis &= 0x3;
-
- if (gate2b->lock)
- spin_lock_irqsave(gate2b->lock, flags);
-
- reg = __raw_readl(gate2b->reg);
- val = (reg >> gate2b->shift) & 0x3;
- reg &= ~(0x3 << gate2b->shift);
- if (val == gate2b->val_en && val != en)
- reg |= en << gate2b->shift;
- else if (val == gate2b->val_dis && val != dis)
- reg |= dis << gate2b->shift;
- __raw_writel(reg, gate2b->reg);
- gate2b->val_en = en;
- gate2b->val_dis = dis;
-
- if (gate2b->lock)
- spin_unlock_irqrestore(gate2b->lock, flags);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(clk_gate2b_set_val);
deleted file mode 100644
@@ -1,221 +0,0 @@
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-
-#include <asm/div64.h>
-
-#include <mach/clock.h>
-
-#define to_clk_pllv2(ck) (container_of(clk, struct clk_pllv2, clk))
-
-/* PLL Register Offsets */
-#define MXC_PLL_DP_CTL 0x00
-#define MXC_PLL_DP_CONFIG 0x04
-#define MXC_PLL_DP_OP 0x08
-#define MXC_PLL_DP_MFD 0x0C
-#define MXC_PLL_DP_MFN 0x10
-#define MXC_PLL_DP_MFNMINUS 0x14
-#define MXC_PLL_DP_MFNPLUS 0x18
-#define MXC_PLL_DP_HFS_OP 0x1C
-#define MXC_PLL_DP_HFS_MFD 0x20
-#define MXC_PLL_DP_HFS_MFN 0x24
-#define MXC_PLL_DP_MFN_TOGC 0x28
-#define MXC_PLL_DP_DESTAT 0x2c
-
-/* PLL Register Bit definitions */
-#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
-#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
-#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
-#define MXC_PLL_DP_CTL_ADE 0x800
-#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
-#define MXC_PLL_DP_CTL_HFSM 0x80
-#define MXC_PLL_DP_CTL_PRE 0x40
-#define MXC_PLL_DP_CTL_UPEN 0x20
-#define MXC_PLL_DP_CTL_RST 0x10
-#define MXC_PLL_DP_CTL_RCP 0x8
-#define MXC_PLL_DP_CTL_PLM 0x4
-#define MXC_PLL_DP_CTL_BRM0 0x2
-#define MXC_PLL_DP_CTL_LRF 0x1
-
-#define MXC_PLL_DP_CONFIG_BIST 0x8
-#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
-#define MXC_PLL_DP_CONFIG_AREN 0x2
-#define MXC_PLL_DP_CONFIG_LDREQ 0x1
-
-#define MXC_PLL_DP_OP_MFI_OFFSET 4
-#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
-#define MXC_PLL_DP_OP_PDF_OFFSET 0
-#define MXC_PLL_DP_OP_PDF_MASK 0xF
-
-#define MXC_PLL_DP_MFD_OFFSET 0
-#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_OFFSET 0x0
-#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
-#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
-#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
-#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
-
-#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
-#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
-
-#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
-
-static unsigned long clk_pllv2_get_rate(struct clk *clk)
-{
- long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
- unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
- void __iomem *pllbase;
- s64 temp;
- unsigned long parent_rate;
- struct clk_pllv2 *pll = to_clk_pllv2(clk);
-
- parent_rate = clk->parent->rate;
-
- pllbase = pll->base;
-
- dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
- pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
- dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
-
- if (pll_hfsm == 0) {
- dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
- dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
- dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
- } else {
- dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
- dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
- dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
- }
- pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
- mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
- mfi = (mfi <= 5) ? 5 : mfi;
- mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
- mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
- /* Sign extend to 32-bits */
- if (mfn >= 0x04000000) {
- mfn |= 0xFC000000;
- mfn_abs = -mfn;
- }
-
- ref_clk = 2 * parent_rate;
- if (dbl != 0)
- ref_clk *= 2;
-
- ref_clk /= (pdf + 1);
- temp = (u64) ref_clk * mfn_abs;
- do_div(temp, mfd + 1);
- if (mfn < 0)
- temp = -temp;
- temp = (ref_clk * mfi) + temp;
-
- return temp;
-}
-
-static int clk_pllv2_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 reg;
- void __iomem *pllbase;
- struct clk_pllv2 *pll = to_clk_pllv2(clk);
-
- long mfi, pdf, mfn, mfd = 999999;
- s64 temp64;
- unsigned long quad_parent_rate;
- unsigned long pll_hfsm, dp_ctl;
- unsigned long parent_rate;
-
- parent_rate = clk->parent->rate;
-
- pllbase = pll->base;
-
- quad_parent_rate = 4 * parent_rate;
- pdf = mfi = -1;
- while (++pdf < 16 && mfi < 5)
- mfi = rate * (pdf+1) / quad_parent_rate;
- if (mfi > 15)
- return -EINVAL;
- pdf--;
-
- temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
- do_div(temp64, quad_parent_rate/1000000);
- mfn = (long)temp64;
-
- dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
- /* use dpdck0_2 */
- __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
- pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
- if (pll_hfsm == 0) {
- reg = mfi << 4 | pdf;
- __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
- __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
- __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
- } else {
- reg = mfi << 4 | pdf;
- __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
- __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
- __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
- }
-
- return 0;
-}
-
-static long clk_pllv2_round_rate(struct clk *clk, unsigned long rate,
- unsigned long *prate)
-{
- *prate = 0;
- return rate;
-}
-
-static int clk_pllv2_enable(struct clk *clk)
-{
- struct clk_pllv2 *pll = to_clk_pllv2(clk);
- u32 reg;
- void __iomem *pllbase;
- int i = 0;
-
- pllbase = pll->base;
- reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
- __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
-
- /* Wait for lock */
- do {
- reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
- if (reg & MXC_PLL_DP_CTL_LRF)
- break;
-
- udelay(1);
- } while (++i < MAX_DPLL_WAIT_TRIES);
-
- if (i == MAX_DPLL_WAIT_TRIES) {
- pr_err("MX5: pll locking failed\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static void clk_pllv2_disable(struct clk *clk)
-{
- struct clk_pllv2 *pll = to_clk_pllv2(clk);
- u32 reg;
- void __iomem *pllbase;
-
- pllbase = pll->base;
- reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
- __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
-}
-
-struct clk_hw_ops clk_pllv2_ops = {
- .enable = clk_pllv2_enable,
- .disable = clk_pllv2_disable,
- .recalc_rate = clk_pllv2_get_rate,
- .round_rate = clk_pllv2_round_rate,
- .set_rate = clk_pllv2_set_rate,
-};
-
new file mode 100644
@@ -0,0 +1,600 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+
+#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
+#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
+#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
+#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
+#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
+#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
+
+/*MX53*/
+#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
+#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
+#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
+#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
+#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
+
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL 0x00
+#define MXC_PLL_DP_CONFIG 0x04
+#define MXC_PLL_DP_OP 0x08
+#define MXC_PLL_DP_MFD 0x0C
+#define MXC_PLL_DP_MFN 0x10
+#define MXC_PLL_DP_MFNMINUS 0x14
+#define MXC_PLL_DP_MFNPLUS 0x18
+#define MXC_PLL_DP_HFS_OP 0x1C
+#define MXC_PLL_DP_HFS_MFD 0x20
+#define MXC_PLL_DP_HFS_MFN 0x24
+#define MXC_PLL_DP_MFN_TOGC 0x28
+#define MXC_PLL_DP_DESTAT 0x2c
+
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
+#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
+#define MXC_PLL_DP_CTL_ADE 0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
+#define MXC_PLL_DP_CTL_HFSM 0x80
+#define MXC_PLL_DP_CTL_PRE 0x40
+#define MXC_PLL_DP_CTL_UPEN 0x20
+#define MXC_PLL_DP_CTL_RST 0x10
+#define MXC_PLL_DP_CTL_RCP 0x8
+#define MXC_PLL_DP_CTL_PLM 0x4
+#define MXC_PLL_DP_CTL_BRM0 0x2
+#define MXC_PLL_DP_CTL_LRF 0x1
+
+#define MXC_PLL_DP_CONFIG_BIST 0x8
+#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
+#define MXC_PLL_DP_CONFIG_AREN 0x2
+#define MXC_PLL_DP_CONFIG_LDREQ 0x1
+
+#define MXC_PLL_DP_OP_MFI_OFFSET 4
+#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
+#define MXC_PLL_DP_OP_PDF_OFFSET 0
+#define MXC_PLL_DP_OP_PDF_MASK 0xF
+
+#define MXC_PLL_DP_MFD_OFFSET 0
+#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_OFFSET 0x0
+#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
+#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
+#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
+#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
+
+#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
+#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
+
+/* Register addresses of CCM*/
+#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00)
+#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04)
+#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08)
+#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C)
+#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10)
+#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14)
+#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18)
+#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C)
+#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20)
+#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24)
+#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28)
+#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C)
+#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30)
+#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34)
+#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38)
+#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C)
+#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40)
+#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44)
+#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48)
+#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C)
+#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50)
+#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54)
+#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58)
+#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C)
+#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60)
+#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64)
+#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68)
+#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C)
+#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70)
+#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74)
+#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
+#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
+#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
+#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84)
+
+#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN (1 << 12)
+#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
+#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
+#define MXC_CCM_CCR_FPM_EN (1 << 8)
+#define MXC_CCM_CCR_OSCNT_OFFSET (0)
+#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
+#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
+#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
+
+/* Define the bits in register CSR */
+#define MXC_CCM_CSR_COSR_READY (1 << 5)
+#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
+#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
+#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
+#define MXC_CCM_CSR_FPM_READY (1 << 1)
+#define MXC_CCM_CSR_REF_EN_B (1 << 0)
+
+/* Define the bits in register CCSR */
+#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
+#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
+#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0
+#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */
+#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
+#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
+#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
+#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
+#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
+#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk,
+ 1: step_clk */
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
+#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
+#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
+#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
+#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
+#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
+#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
+#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
+#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
+#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
+#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
+#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
+#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
+#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
+#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
+#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
+#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
+#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
+
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
+#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
+#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
+#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
+#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
+#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
+
+/* Define the bits in register CSCDR1 */
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
+
+/* Define the bits in register CS1CDR and CS2CDR */
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
+
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
+
+/* Define the bits in register CDCDR */
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
+#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
+#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
+#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
+
+/* Define the bits in register CHSCCDR */
+#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
+
+/* Define the bits in register CSCDR3 */
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
+
+/* Define the bits in register CSCDR4 */
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
+
+/* Define the bits in register CDHIPR */
+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
+#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
+#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
+#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
+#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
+#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
+#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
+#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
+
+/* Define the bits in register CDCR */
+#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
+#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
+#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
+#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
+#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
+#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
+#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
+#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
+#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
+#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
+#define MXC_CCM_CLPCR_LPM_OFFSET (0)
+#define MXC_CCM_CLPCR_LPM_MASK (0x3)
+
+/* Define the bits in register CISR */
+#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
+#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
+#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
+#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
+#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
+#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
+#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
+#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
+#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
+#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
+#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
+#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
+#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
+#define MXC_CCM_CISR_LRF_PLL1 (0x1)
+
+/* Define the bits in register CIMR */
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
+#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
+#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
+#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
+#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
+#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
+#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
+#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
+#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
+#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
+#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
+#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
+#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
+
+/* Define the bits in register CCOSR */
+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
+#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
+
+/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
+#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
+
+/* Define the bits in registers CCGRx */
+#define MXC_CCM_CCGRx_CG_MASK 0x3
+#define MXC_CCM_CCGRx_MOD_OFF 0x0
+#define MXC_CCM_CCGRx_MOD_ON 0x3
+#define MXC_CCM_CCGRx_MOD_IDLE 0x1
+
+#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30)
+#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28)
+#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26)
+#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24)
+#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22)
+#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20)
+#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18)
+#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16)
+#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10)
+#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8)
+#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6)
+#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4)
+#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2)
+#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0)
+
+#define MXC_CCM_CCGRx_CG15_OFFSET 30
+#define MXC_CCM_CCGRx_CG14_OFFSET 28
+#define MXC_CCM_CCGRx_CG13_OFFSET 26
+#define MXC_CCM_CCGRx_CG12_OFFSET 24
+#define MXC_CCM_CCGRx_CG11_OFFSET 22
+#define MXC_CCM_CCGRx_CG10_OFFSET 20
+#define MXC_CCM_CCGRx_CG9_OFFSET 18
+#define MXC_CCM_CCGRx_CG8_OFFSET 16
+#define MXC_CCM_CCGRx_CG7_OFFSET 14
+#define MXC_CCM_CCGRx_CG6_OFFSET 12
+#define MXC_CCM_CCGRx_CG5_OFFSET 10
+#define MXC_CCM_CCGRx_CG4_OFFSET 8
+#define MXC_CCM_CCGRx_CG3_OFFSET 6
+#define MXC_CCM_CCGRx_CG2_OFFSET 4
+#define MXC_CCM_CCGRx_CG1_OFFSET 2
+#define MXC_CCM_CCGRx_CG0_OFFSET 0
+
+#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
+#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
+#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
+#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
+#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
+#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
+#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
+#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
+#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
+#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
+#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
+#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
+#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
+
+/* CORTEXA8 platform */
+#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
+#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
+#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
+#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
+#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
+#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
+#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
+#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
+#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
+
+/* DVFS CORE */
+#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
+#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
+#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
+#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
+#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
+#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
+#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
+#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
+#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
+#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
+#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
+#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
+#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
+#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
+#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
+#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
+#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
+
+/* GPC */
+#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
+#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
+#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
+#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
+#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)
+#define MXC_GPC_PGR_ARMPG_OFFSET 8
+#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
+
+/* PGC */
+#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
+#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
+#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
+#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
+#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
+#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
+
+#define MXC_PGCR_PCR 1
+#define MXC_SRPGCR_PCR 1
+#define MXC_EMPGCR_PCR 1
+#define MXC_PGSR_PSR 1
+
+
+#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
+#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
+
+/* SRPG */
+#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
+#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
+#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
+
+#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
+#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
+#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
+
+#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
+#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
+#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
+
+#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
+#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
+#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
+
+#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
+#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
+#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
+
+#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
+#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
+#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
+
+#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
@@ -36,3 +36,6 @@ config GENERIC_CLK_DEBUG
tree structure as well. Each directory contains read-only
members that export information specific to that clk node:
clk_rate, clk_flags, clk_prepare_count & clk_enable_count.
+
+
+source "drivers/clk/imx/Kconfig"
@@ -4,3 +4,5 @@ obj-$(CONFIG_GENERIC_CLK) += clk.o
obj-$(CONFIG_GENERIC_CLK_BASIC) += clk-basic.o
obj-$(CONFIG_GENERIC_CLK_DIVIDER) += clk-divider.o
obj-$(CONFIG_GENERIC_CLK_MUX) += clk-mux.o
+
+obj-y += imx/
new file mode 100644
@@ -0,0 +1,21 @@
+if ARCH_MXC
+
+config IMX_CLK_PLLV2
+ bool
+ depends on GENERIC_CLK
+
+config IMX_CLK_GATE2B
+ bool
+ depends on GENERIC_CLK
+
+config IMX51_IMX53_CLK
+ bool
+ select GENERIC_CLK
+ select GENERIC_CLK_FIXED
+ select GENERIC_CLK_DIVIDER
+ select GENERIC_CLK_MUX
+ select GENERIC_CLK_DUMMY
+ select IMX_CLK_PLLV2
+ select IMX_CLK_GATE2B
+
+endif
new file mode 100644
@@ -0,0 +1,3 @@
+obj-$(CONFIG_IMX_CLK_PLLV2) += clk-pllv2.o
+obj-$(CONFIG_IMX_CLK_GATE2B) += clk-gate2b.o
+obj-$(CONFIG_IMX51_IMX53_CLK) += clock-imx51-imx53.o
new file mode 100644
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <mach/clock.h>
+
+#define to_clk_gate2b(ck) container_of(ck, struct clk_gate2b, clk)
+
+static int clk_gate2b_enable(struct clk *clk)
+{
+ struct clk_gate2b *gate2b = to_clk_gate2b(clk);
+ unsigned long flags;
+ u32 reg;
+
+ if (gate2b->lock)
+ spin_lock_irqsave(gate2b->lock, flags);
+
+ reg = __raw_readl(gate2b->reg);
+ reg &= ~(0x3 << gate2b->shift);
+ reg |= gate2b->val_en << gate2b->shift;
+ __raw_writel(reg, gate2b->reg);
+
+ if (gate2b->lock)
+ spin_unlock_irqrestore(gate2b->lock, flags);
+
+ return 0;
+}
+
+static void clk_gate2b_disable(struct clk *clk)
+{
+ struct clk_gate2b *gate2b = to_clk_gate2b(clk);
+ unsigned long flags;
+ u32 reg;
+
+ if (gate2b->lock)
+ spin_lock_irqsave(gate2b->lock, flags);
+
+ reg = __raw_readl(gate2b->reg);
+ reg &= ~(0x3 << gate2b->shift);
+ reg |= gate2b->val_dis << gate2b->shift;
+ __raw_writel(reg, gate2b->reg);
+
+ if (gate2b->lock)
+ spin_unlock_irqrestore(gate2b->lock, flags);
+
+}
+
+struct clk_hw_ops clk_gate2b_ops = {
+ .enable = clk_gate2b_enable,
+ .disable = clk_gate2b_disable,
+};
+EXPORT_SYMBOL_GPL(clk_gate2b_ops);
+
+int clk_gate2b_set_val(struct clk *clk, int en, int dis)
+{
+ struct clk_gate2b *gate2b = to_clk_gate2b(clk);
+ unsigned long flags;
+ u32 reg, val;
+
+ en &= 0x3;
+ dis &= 0x3;
+
+ if (gate2b->lock)
+ spin_lock_irqsave(gate2b->lock, flags);
+
+ reg = __raw_readl(gate2b->reg);
+ val = (reg >> gate2b->shift) & 0x3;
+ reg &= ~(0x3 << gate2b->shift);
+ if (val == gate2b->val_en && val != en)
+ reg |= en << gate2b->shift;
+ else if (val == gate2b->val_dis && val != dis)
+ reg |= dis << gate2b->shift;
+ __raw_writel(reg, gate2b->reg);
+ gate2b->val_en = en;
+ gate2b->val_dis = dis;
+
+ if (gate2b->lock)
+ spin_unlock_irqrestore(gate2b->lock, flags);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(clk_gate2b_set_val);
new file mode 100644
@@ -0,0 +1,221 @@
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include <asm/div64.h>
+
+#include <mach/clock.h>
+
+#define to_clk_pllv2(ck) (container_of(clk, struct clk_pllv2, clk))
+
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL 0x00
+#define MXC_PLL_DP_CONFIG 0x04
+#define MXC_PLL_DP_OP 0x08
+#define MXC_PLL_DP_MFD 0x0C
+#define MXC_PLL_DP_MFN 0x10
+#define MXC_PLL_DP_MFNMINUS 0x14
+#define MXC_PLL_DP_MFNPLUS 0x18
+#define MXC_PLL_DP_HFS_OP 0x1C
+#define MXC_PLL_DP_HFS_MFD 0x20
+#define MXC_PLL_DP_HFS_MFN 0x24
+#define MXC_PLL_DP_MFN_TOGC 0x28
+#define MXC_PLL_DP_DESTAT 0x2c
+
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
+#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
+#define MXC_PLL_DP_CTL_ADE 0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
+#define MXC_PLL_DP_CTL_HFSM 0x80
+#define MXC_PLL_DP_CTL_PRE 0x40
+#define MXC_PLL_DP_CTL_UPEN 0x20
+#define MXC_PLL_DP_CTL_RST 0x10
+#define MXC_PLL_DP_CTL_RCP 0x8
+#define MXC_PLL_DP_CTL_PLM 0x4
+#define MXC_PLL_DP_CTL_BRM0 0x2
+#define MXC_PLL_DP_CTL_LRF 0x1
+
+#define MXC_PLL_DP_CONFIG_BIST 0x8
+#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
+#define MXC_PLL_DP_CONFIG_AREN 0x2
+#define MXC_PLL_DP_CONFIG_LDREQ 0x1
+
+#define MXC_PLL_DP_OP_MFI_OFFSET 4
+#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
+#define MXC_PLL_DP_OP_PDF_OFFSET 0
+#define MXC_PLL_DP_OP_PDF_MASK 0xF
+
+#define MXC_PLL_DP_MFD_OFFSET 0
+#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_OFFSET 0x0
+#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
+#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
+#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
+#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
+
+#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
+#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
+
+#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
+
+static unsigned long clk_pllv2_get_rate(struct clk *clk)
+{
+ long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
+ unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
+ void __iomem *pllbase;
+ s64 temp;
+ unsigned long parent_rate;
+ struct clk_pllv2 *pll = to_clk_pllv2(clk);
+
+ parent_rate = clk->parent->rate;
+
+ pllbase = pll->base;
+
+ dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+ pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+ dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
+
+ if (pll_hfsm == 0) {
+ dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
+ dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
+ dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
+ } else {
+ dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
+ dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
+ dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
+ }
+ pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
+ mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
+ mfi = (mfi <= 5) ? 5 : mfi;
+ mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
+ mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
+ /* Sign extend to 32-bits */
+ if (mfn >= 0x04000000) {
+ mfn |= 0xFC000000;
+ mfn_abs = -mfn;
+ }
+
+ ref_clk = 2 * parent_rate;
+ if (dbl != 0)
+ ref_clk *= 2;
+
+ ref_clk /= (pdf + 1);
+ temp = (u64) ref_clk * mfn_abs;
+ do_div(temp, mfd + 1);
+ if (mfn < 0)
+ temp = -temp;
+ temp = (ref_clk * mfi) + temp;
+
+ return temp;
+}
+
+static int clk_pllv2_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ void __iomem *pllbase;
+ struct clk_pllv2 *pll = to_clk_pllv2(clk);
+
+ long mfi, pdf, mfn, mfd = 999999;
+ s64 temp64;
+ unsigned long quad_parent_rate;
+ unsigned long pll_hfsm, dp_ctl;
+ unsigned long parent_rate;
+
+ parent_rate = clk->parent->rate;
+
+ pllbase = pll->base;
+
+ quad_parent_rate = 4 * parent_rate;
+ pdf = mfi = -1;
+ while (++pdf < 16 && mfi < 5)
+ mfi = rate * (pdf+1) / quad_parent_rate;
+ if (mfi > 15)
+ return -EINVAL;
+ pdf--;
+
+ temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
+ do_div(temp64, quad_parent_rate/1000000);
+ mfn = (long)temp64;
+
+ dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+ /* use dpdck0_2 */
+ __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
+ pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+ if (pll_hfsm == 0) {
+ reg = mfi << 4 | pdf;
+ __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
+ __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
+ __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
+ } else {
+ reg = mfi << 4 | pdf;
+ __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
+ __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
+ __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
+ }
+
+ return 0;
+}
+
+static long clk_pllv2_round_rate(struct clk *clk, unsigned long rate,
+ unsigned long *prate)
+{
+ *prate = 0;
+ return rate;
+}
+
+static int clk_pllv2_enable(struct clk *clk)
+{
+ struct clk_pllv2 *pll = to_clk_pllv2(clk);
+ u32 reg;
+ void __iomem *pllbase;
+ int i = 0;
+
+ pllbase = pll->base;
+ reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
+ __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+
+ /* Wait for lock */
+ do {
+ reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+ if (reg & MXC_PLL_DP_CTL_LRF)
+ break;
+
+ udelay(1);
+ } while (++i < MAX_DPLL_WAIT_TRIES);
+
+ if (i == MAX_DPLL_WAIT_TRIES) {
+ pr_err("MX5: pll locking failed\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void clk_pllv2_disable(struct clk *clk)
+{
+ struct clk_pllv2 *pll = to_clk_pllv2(clk);
+ u32 reg;
+ void __iomem *pllbase;
+
+ pllbase = pll->base;
+ reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
+ __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+}
+
+struct clk_hw_ops clk_pllv2_ops = {
+ .enable = clk_pllv2_enable,
+ .disable = clk_pllv2_disable,
+ .recalc_rate = clk_pllv2_get_rate,
+ .round_rate = clk_pllv2_round_rate,
+ .set_rate = clk_pllv2_set_rate,
+};
+
new file mode 100644
@@ -0,0 +1,639 @@
+/*
+ * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+
+#include <asm/div64.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/clock.h>
+#include <mach/crm_mx51_mx53_regs.h>
+
+struct clk_dummy {
+ struct clk clk;
+};
+
+static struct clk_hw_ops dumy_ops;
+static struct clk_dummy dummy = {
+ .clk = {
+ .name = "dummy",
+ .ops = &dumy_ops,
+ },
+};
+
+static DEFINE_CLK_FIXED(ckil, 0);
+static DEFINE_CLK_FIXED(osc, 0);
+static DEFINE_CLK_FIXED(ckih1, 0);
+static DEFINE_CLK_FIXED(ckih2, 0);
+
+static DEFINE_CLK_PLLV2(pll1, &osc.clk, MX51_DPLL1_BASE);
+static DEFINE_CLK_PLLV2(pll2, &osc.clk, MX51_DPLL2_BASE);
+static DEFINE_CLK_PLLV2(pll3, &osc.clk, MX51_DPLL3_BASE);
+static DEFINE_CLK_PLLV2(pll4, &osc.clk, MX53_DPLL4_BASE);
+
+static struct clk_dummy dummy;
+
+/* Low-power Audio Playback Mode clock */
+static struct clk *lp_apm_sel[] = {
+ &osc.clk,
+ NULL,
+};
+static IMX_DEFINE_CLK_MUX(lp_apm, MXC_CCM_CCSR, 9, 1, lp_apm_sel);
+
+static IMX_DEFINE_CLK_DIVIDER(step_pll2_div, &pll2.clk, 0, MXC_CCM_CCSR, 5, 2);
+
+static IMX_DEFINE_CLK_DIVIDER(step_pll3_div, &pll3.clk, 0, MXC_CCM_CCSR, 3, 2);
+
+static struct clk *step_clk_sel[] = {
+ &lp_apm.clk,
+ NULL,
+ &step_pll2_div.clk,
+ &step_pll3_div.clk,
+};
+static IMX_DEFINE_CLK_MUX(step_clk, MXC_CCM_CCSR, 7, 2, step_clk_sel);
+
+static struct clk *pll1_sw_sel[] = {
+ &pll1.clk,
+ &step_clk.clk,
+};
+static IMX_DEFINE_CLK_MUX(pll1_sw, MXC_CCM_CCSR, 2, 1, pll1_sw_sel);
+
+static struct clk *pll2_sw_sel[] = {
+ &pll2.clk,
+ NULL,
+};
+static IMX_DEFINE_CLK_MUX(pll2_sw, MXC_CCM_CCSR, 1, 1, pll2_sw_sel);
+
+static struct clk *pll3_sw_sel[] = {
+ &pll3.clk,
+ NULL,
+};
+static IMX_DEFINE_CLK_MUX(pll3_sw, MXC_CCM_CCSR, 0, 1, pll3_sw_sel);
+
+static struct clk *pll4_sw_sel[] = {
+ &pll4.clk,
+ NULL,
+};
+static IMX_DEFINE_CLK_MUX(pll4_sw, MXC_CCM_CCSR, 9, 1, pll4_sw_sel);
+
+
+/* This is used multiple times */
+static struct clk *standard_pll_sel_clks[] = {
+ &pll1_sw.clk,
+ &pll2_sw.clk,
+ &pll3_sw.clk,
+ &lp_apm.clk,
+};
+
+static struct clk *periph_apm_sel[] = {
+ &pll1_sw.clk,
+ &pll3_sw.clk,
+ &lp_apm.clk,
+};
+static IMX_DEFINE_CLK_MUX(periph_apm, MXC_CCM_CBCMR, 12, 2, periph_apm_sel);
+
+static struct clk *main_bus_sel[] = {
+ &pll2_sw.clk,
+ &periph_apm.clk,
+};
+static IMX_DEFINE_CLK_MUX(main_bus, MXC_CCM_CBCDR, 25, 1, main_bus_sel);
+
+static IMX_DEFINE_CLK_DIVIDER(ahb_root, &main_bus.clk, 0, MXC_CCM_CBCDR, 10, 3);
+static IMX_DEFINE_CLK_DIVIDER(ipg, &ahb_root.clk, 0, MXC_CCM_CBCDR, 8, 2);
+
+static struct clk *perclk_lp_apm_sel[] = {
+ &main_bus.clk,
+ &lp_apm.clk,
+};
+static IMX_DEFINE_CLK_MUX(perclk_lp_apm, MXC_CCM_CBCMR, 1, 1, perclk_lp_apm_sel);
+
+static IMX_DEFINE_CLK_DIVIDER(perclk_pred1, &perclk_lp_apm.clk, 0, MXC_CCM_CBCDR, 6, 2);
+static IMX_DEFINE_CLK_DIVIDER(perclk_pred2, &perclk_pred1.clk, 0, MXC_CCM_CBCDR, 3, 3);
+static IMX_DEFINE_CLK_DIVIDER(perclk_podf, &perclk_pred2.clk, CLK_PARENT_SET_RATE, MXC_CCM_CBCDR, 0, 3);
+
+static struct clk *ipg_perclk_sel[] = {
+ &perclk_podf.clk,
+ &ipg.clk,
+};
+static IMX_DEFINE_CLK_MUX(ipg_perclk, MXC_CCM_CBCMR, 0, 1, ipg_perclk_sel);
+
+static IMX_DEFINE_CLK_DIVIDER(axi_a, &main_bus.clk, 0, MXC_CCM_CBCDR, 16, 3);
+static IMX_DEFINE_CLK_DIVIDER(axi_b, &main_bus.clk, 0, MXC_CCM_CBCDR, 19, 3);
+
+static struct clk *emi_slow_sel_clks[] = {
+ &main_bus.clk,
+ &ahb_root.clk,
+};
+static IMX_DEFINE_CLK_MUX(emi_sel, MXC_CCM_CBCDR, 26, 1, emi_slow_sel_clks);
+static IMX_DEFINE_CLK_DIVIDER(emi_slow_podf, &emi_sel.clk, 0, MXC_CCM_CBCDR, 22, 3);
+static IMX_DEFINE_CLK_DIVIDER(nfc_podf, &emi_slow_podf.clk, 0, MXC_CCM_CBCDR, 13, 3);
+
+static struct clk *xpu_sel[] = {
+ &axi_a.clk,
+ &axi_b.clk,
+ &emi_slow_podf.clk,
+ &ahb_root.clk,
+};
+static IMX_DEFINE_CLK_MUX(gpu2d, MXC_CCM_CBCMR, 16, 2, xpu_sel);
+static IMX_DEFINE_CLK_MUX(arm_axi, MXC_CCM_CBCMR, 8, 2, xpu_sel);
+static IMX_DEFINE_CLK_MUX(ipu_hsp, MXC_CCM_CBCMR, 6, 2, xpu_sel);
+static IMX_DEFINE_CLK_MUX(gpu, MXC_CCM_CBCMR, 4, 2, xpu_sel);
+static IMX_DEFINE_CLK_MUX(vpu_axi_root, MXC_CCM_CBCMR, 14, 2, xpu_sel);
+static IMX_DEFINE_CLK_MUX(ddr_root, MXC_CCM_CBCMR, 10, 2, xpu_sel);
+
+static IMX_DEFINE_CLK_DIVIDER(ddr_hf_mx51, &pll1_sw.clk, 0, MXC_CCM_CBCDR, 27, 3);
+static struct clk *ddr_hf_sel[] = {
+ &ddr_root.clk,
+ &ddr_hf_mx51.clk,
+};
+static IMX_DEFINE_CLK_MUX(ddr_root_mx51, MXC_CCM_CBCDR, 30, 1, ddr_hf_sel);
+
+static IMX_DEFINE_CLK_MUX(uart_sel, MXC_CCM_CSCMR1, 24, 2, standard_pll_sel_clks);
+static IMX_DEFINE_CLK_DIVIDER(uart_pred, &uart_sel.clk, 0, MXC_CCM_CSCDR1, 3, 3);
+static IMX_DEFINE_CLK_DIVIDER(uart_root, &uart_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CSCDR1, 0, 3);
+
+static IMX_DEFINE_CLK_MUX(esdhc1_sel, MXC_CCM_CSCMR1, 20, 2, standard_pll_sel_clks);
+static IMX_DEFINE_CLK_DIVIDER(esdhc1_pred, &esdhc1_sel.clk, 0, MXC_CCM_CSCDR1, 16, 3);
+static IMX_DEFINE_CLK_DIVIDER(esdhc1_podf, &esdhc1_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CSCDR1, 11, 3);
+
+/* This is routed to esdhc3 in the i.MX53 datasheet */
+static IMX_DEFINE_CLK_MUX(esdhc2_sel, MXC_CCM_CSCMR1, 16, 2, standard_pll_sel_clks);
+static IMX_DEFINE_CLK_DIVIDER(esdhc2_pred, &esdhc2_sel.clk, 0, MXC_CCM_CSCDR1, 22, 3);
+static IMX_DEFINE_CLK_DIVIDER(esdhc2_podf, &esdhc2_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CSCDR1, 19, 3);
+
+static struct clk *esdhc3_sel_clks[] = {
+ &esdhc1_podf.clk,
+ &esdhc2_podf.clk,
+};
+static IMX_DEFINE_CLK_MUX(esdhc3_sel, MXC_CCM_CSCMR1, 19, 1, esdhc3_sel_clks);
+
+static struct clk *esdhc4_sel_clks[] = {
+ &esdhc1_podf.clk,
+ &esdhc2_podf.clk,
+};
+static IMX_DEFINE_CLK_MUX(esdhc4_sel, MXC_CCM_CSCMR1, 18, 1, esdhc4_sel_clks);
+
+static struct clk *ssi_apm_sel[] = {
+ &ckih1.clk,
+ &lp_apm.clk,
+ &ckih2.clk,
+};
+static IMX_DEFINE_CLK_MUX(ssi_lp_apm, MXC_CCM_CSCMR1, 8, 2, ssi_apm_sel);
+static IMX_DEFINE_CLK_MUX(ssi1_clk_sel, MXC_CCM_CSCMR1, 14, 2, standard_pll_sel_clks);
+static IMX_DEFINE_CLK_DIVIDER(ssi1_clk_pred, &ssi1_clk_sel.clk, 0, MXC_CCM_CS1CDR, 6, 3);
+static IMX_DEFINE_CLK_DIVIDER(ssi1_clk, &ssi1_clk_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CS1CDR, 0, 6);
+static IMX_DEFINE_CLK_MUX(ssi2_clk_sel, MXC_CCM_CSCMR1, 12, 2, standard_pll_sel_clks);
+static IMX_DEFINE_CLK_DIVIDER(ssi2_clk_pred, &ssi2_clk_sel.clk, 0, MXC_CCM_CS2CDR, 6, 3);
+static IMX_DEFINE_CLK_DIVIDER(ssi2_clk, &ssi2_clk_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CS2CDR, 0, 6);
+static struct clk *ssi3_clk_sel[] = {
+ &ssi1_clk.clk,
+ &ssi2_clk.clk,
+};
+static IMX_DEFINE_CLK_MUX(ssi3_clk, MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sel);
+
+static IMX_DEFINE_CLK_MUX(ecspi_sel, MXC_CCM_CSCMR1, 4, 2, standard_pll_sel_clks);
+static IMX_DEFINE_CLK_DIVIDER(ecspi_pred, &ecspi_sel.clk, 0, MXC_CCM_CSCDR2, 25, 3);
+static IMX_DEFINE_CLK_DIVIDER(ecspi_podf, &ecspi_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CSCDR2, 19, 6);
+
+static IMX_DEFINE_CLK_MUX(usboh3_sel, MXC_CCM_CSCMR1, 22, 2, standard_pll_sel_clks);
+static IMX_DEFINE_CLK_DIVIDER(usboh3_pred, &usboh3_sel.clk, 0, MXC_CCM_CSCDR1, 8, 3);
+static IMX_DEFINE_CLK_DIVIDER(usboh3_podf, &usboh3_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CSCDR1, 6, 2);
+
+static IMX_DEFINE_CLK_DIVIDER(usb_phy_pred, &pll3_sw.clk, 0, MXC_CCM_CDCDR, 3, 3);
+static IMX_DEFINE_CLK_DIVIDER(usb_phy_podf, &usb_phy_pred.clk, CLK_PARENT_SET_RATE, MXC_CCM_CDCDR, 0, 3);
+static struct clk *usb_phy_sel_clks[] = {
+ &osc.clk,
+ &usb_phy_podf.clk,
+};
+static IMX_DEFINE_CLK_MUX(usb_phy_sel, MXC_CCM_CSCMR1, 26, 1, usb_phy_sel_clks);
+
+static IMX_DEFINE_CLK_DIVIDER(cpu_podf, &pll1_sw.clk, 0, MXC_CCM_CACRR, 0, 3);
+
+static struct clk *ipu_di0_sel_clks[] = {
+ &pll3_sw.clk,
+ &osc.clk,
+ &ckih1.clk,
+ NULL, /* &tve_di.clk */
+ NULL, /* ipp di0 (iomux) */
+ NULL, /* ldp di0 */
+};
+static IMX_DEFINE_CLK_MUX(ipu_di0_sel, MXC_CCM_CSCMR2, 26, 3, ipu_di0_sel_clks);
+
+static struct clk *ipu_di1_sel_clks[] = {
+ &pll3_sw.clk,
+ &osc.clk,
+ &ckih1.clk,
+ NULL, /* &tve_di.clk */
+ NULL, /* ipp di1 (iomux) */
+ NULL, /* ldp di1 */
+};
+static IMX_DEFINE_CLK_MUX(ipu_di1_sel, MXC_CCM_CSCMR2, 29, 3, ipu_di1_sel_clks);
+
+static struct clk *tve_ext_sel_clks[] = {
+ &osc.clk,
+ &ckih1.clk,
+};
+static IMX_DEFINE_CLK_MUX(tve_ext_sel, MXC_CCM_CSCMR1, 6, 1, tve_ext_sel_clks);
+
+static IMX_DEFINE_CLK_DIVIDER(tve_pred, &pll3_sw.clk, 0, MXC_CCM_CDCDR, 28, 3);
+
+static struct clk *tve_sel_clks[] = {
+ &tve_pred.clk,
+ &tve_ext_sel.clk,
+};
+static IMX_DEFINE_CLK_MUX(tve_sel, MXC_CCM_CSCMR1, 7, 1, tve_sel_clks);
+
+static DEFINE_CLK_GATE2B(ahbmux1, &ipg.clk, MXC_CCM_CCGR0, 8);
+static DEFINE_CLK_GATE2B(aips_tz1, &ipg.clk, MXC_CCM_CCGR0, 12);
+static DEFINE_CLK_GATE2B(aips_tz2, &ipg.clk, MXC_CCM_CCGR0, 13);
+static DEFINE_CLK_GATE2B(ahb_max, &ipg.clk, MXC_CCM_CCGR0, 14);
+static DEFINE_CLK_GATE2B(iim_gate, &ipg.clk, MXC_CCM_CCGR0, 15);
+
+static DEFINE_CLK_GATE2B(uart1_ipg_gate, &ipg.clk, MXC_CCM_CCGR1, 3);
+static DEFINE_CLK_GATE2B(uart1_per_gate, &uart_root.clk, MXC_CCM_CCGR1, 4);
+static DEFINE_CLK_GATE2B(uart2_ipg_gate, &ipg.clk, MXC_CCM_CCGR1, 5);
+static DEFINE_CLK_GATE2B(uart2_per_gate, &uart_root.clk, MXC_CCM_CCGR1, 6);
+static DEFINE_CLK_GATE2B(uart3_ipg_gate, &ipg.clk, MXC_CCM_CCGR1, 7);
+static DEFINE_CLK_GATE2B(uart3_per_gate, &uart_root.clk, MXC_CCM_CCGR1, 8);
+static DEFINE_CLK_GATE2B(i2c1_gate, &ipg_perclk.clk, MXC_CCM_CCGR1, 9);
+static DEFINE_CLK_GATE2B(i2c2_gate, &ipg_perclk.clk, MXC_CCM_CCGR1, 10);
+static DEFINE_CLK_GATE2B(hsi2c_gate, &ipg.clk, MXC_CCM_CCGR1, 11);
+
+static DEFINE_CLK_GATE2B(mx51_usb_phy_gate, &usb_phy_sel.clk, MXC_CCM_CCGR2, 0);
+static DEFINE_CLK_GATE2B(gpt_ipg_gate, &ipg.clk, MXC_CCM_CCGR2, 10);
+static DEFINE_CLK_GATE2B(pwm1_ipg_gate, &ipg.clk, MXC_CCM_CCGR2, 5);
+static DEFINE_CLK_GATE2B(pwm1_hf_gate, &ipg_perclk.clk, MXC_CCM_CCGR2, 6);
+static DEFINE_CLK_GATE2B(pwm2_ipg_gate, &ipg.clk, MXC_CCM_CCGR2, 7);
+static DEFINE_CLK_GATE2B(pwm2_hf_gate, &ipg_perclk.clk, MXC_CCM_CCGR2, 8);
+static DEFINE_CLK_GATE2B(gpt_gate, &ipg.clk, MXC_CCM_CCGR2, 9);
+static DEFINE_CLK_GATE2B(fec_gate, &ipg.clk, MXC_CCM_CCGR2, 12);
+static DEFINE_CLK_GATE2B(usboh3_ahb_gate, &ipg.clk, MXC_CCM_CCGR2, 13);
+static DEFINE_CLK_GATE2B(usboh3_gate, &usboh3_podf.clk, MXC_CCM_CCGR2, 14);
+static DEFINE_CLK_GATE2B(tve_gate, &tve_sel.clk, MXC_CCM_CCGR2, 15);
+
+static DEFINE_CLK_GATE2B(esdhc1_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 0);
+static DEFINE_CLK_GATE2B(esdhc1_per_gate, &esdhc1_podf.clk, MXC_CCM_CCGR3, 1);
+static DEFINE_CLK_GATE2B(esdhc2_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 2);
+static DEFINE_CLK_GATE2B(esdhc2_per_gate, &esdhc2_podf.clk, MXC_CCM_CCGR3, 3);
+static DEFINE_CLK_GATE2B(esdhc3_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 4);
+static DEFINE_CLK_GATE2B(esdhc3_per_gate, &esdhc3_sel.clk, MXC_CCM_CCGR3, 5);
+static DEFINE_CLK_GATE2B(esdhc4_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 6);
+static DEFINE_CLK_GATE2B(esdhc4_per_gate, &esdhc4_sel.clk, MXC_CCM_CCGR3, 7);
+static DEFINE_CLK_GATE2B(ssi1_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 8);
+static DEFINE_CLK_GATE2B(ssi1_gate, &ssi1_clk.clk, MXC_CCM_CCGR3, 9);
+static DEFINE_CLK_GATE2B(ssi2_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 10);
+static DEFINE_CLK_GATE2B(ssi2_gate, &ssi2_clk.clk, MXC_CCM_CCGR3, 11);
+static DEFINE_CLK_GATE2B(ssi3_ipg_gate, &ipg.clk, MXC_CCM_CCGR3, 12);
+static DEFINE_CLK_GATE2B(ssi3_gate, &ssi3_clk.clk, MXC_CCM_CCGR3, 13);
+
+static DEFINE_CLK_GATE2B(mx51_mipi_hsc1_gate, &ipg.clk, MXC_CCM_CCGR4, 3);
+static DEFINE_CLK_GATE2B(mx51_mipi_hsc2_gate, &ipg.clk, MXC_CCM_CCGR4, 4);
+static DEFINE_CLK_GATE2B(mx51_mipi_esc_gate, &ipg.clk, MXC_CCM_CCGR4, 5);
+static DEFINE_CLK_GATE2B(mx51_mipi_hsp_gate, &ipg.clk, MXC_CCM_CCGR4, 6);
+
+static DEFINE_CLK_GATE2B(mx53_usb_phy1_gate, &usb_phy_sel.clk, MXC_CCM_CCGR4, 5);
+static DEFINE_CLK_GATE2B(mx53_usb_phy2_gate, &usb_phy_sel.clk, MXC_CCM_CCGR4, 6);
+static DEFINE_CLK_GATE2B(ecspi1_ipg_gate, &ipg.clk, MXC_CCM_CCGR4, 9);
+static DEFINE_CLK_GATE2B(ecspi1_per_gate, &ecspi_podf.clk, MXC_CCM_CCGR4, 10);
+static DEFINE_CLK_GATE2B(ecspi2_ipg_gate, &ipg.clk, MXC_CCM_CCGR4, 11);
+static DEFINE_CLK_GATE2B(ecspi2_per_gate, &ecspi_podf.clk, MXC_CCM_CCGR4, 12);
+static DEFINE_CLK_GATE2B(cspi_ipg_gate, &ipg.clk, MXC_CCM_CCGR4, 13);
+static DEFINE_CLK_GATE2B(sdma_gate, &ipg.clk, MXC_CCM_CCGR4, 15);
+
+static DEFINE_CLK_GATE2B(ipu_gate, &ipu_hsp.clk, MXC_CCM_CCGR5, 5);
+static DEFINE_CLK_GATE2B(emi_fast_gate, &dummy.clk, MXC_CCM_CCGR5, 7);
+static DEFINE_CLK_GATE2B(emi_slow_gate, &emi_slow_podf.clk, MXC_CCM_CCGR5, 8);
+static DEFINE_CLK_GATE2B(nfc_gate, &nfc_podf.clk, MXC_CCM_CCGR5, 10);
+
+static DEFINE_CLK_GATE2B(ipu_di0_gate, &ipu_di0_sel.clk, MXC_CCM_CCGR6, 5);
+static DEFINE_CLK_GATE2B(ipu_di1_gate, &ipu_di1_sel.clk, MXC_CCM_CCGR6, 6);
+
+#define _REGISTER_CLKDEV(d, n, c) \
+ { \
+ .dev_id = d, \
+ .con_id = n, \
+ .clk = c, \
+ },
+
+static struct clk_lookup mx5_lookups[] = {
+ _REGISTER_CLKDEV("imx21-uart.0", NULL, &uart1_per_gate.clk)
+ _REGISTER_CLKDEV("imx21-uart.1", NULL, &uart2_per_gate.clk)
+ _REGISTER_CLKDEV("imx21-uart.2", NULL, &uart3_per_gate.clk)
+ _REGISTER_CLKDEV("mxc_pwm.0", "pwm", &pwm1_ipg_gate.clk)
+ _REGISTER_CLKDEV("mxc_pwm.1", "pwm", &pwm2_ipg_gate.clk)
+ _REGISTER_CLKDEV("imx-i2c.0", NULL, &i2c1_gate.clk)
+ _REGISTER_CLKDEV("imx-i2c.1", NULL, &i2c2_gate.clk)
+ _REGISTER_CLKDEV("mxc-ehci.0", "usb", &usboh3_gate.clk)
+ _REGISTER_CLKDEV("mxc-ehci.0", "usb_ahb", &usboh3_ahb_gate.clk)
+ _REGISTER_CLKDEV("mxc-ehci.0", "usb_phy1", &mx53_usb_phy1_gate.clk)
+ _REGISTER_CLKDEV("mxc-ehci.1", "usb", &usboh3_gate.clk)
+ _REGISTER_CLKDEV("mxc-ehci.1", "usb_ahb", &usboh3_ahb_gate.clk)
+ _REGISTER_CLKDEV("mxc-ehci.2", "usb", &usboh3_gate.clk)
+ _REGISTER_CLKDEV("mxc-ehci.2", "usb_ahb", &usboh3_ahb_gate.clk)
+ _REGISTER_CLKDEV("fsl-usb2-udc", "usb", &usboh3_gate.clk)
+ _REGISTER_CLKDEV("fsl-usb2-udc", "usb_ahb", &usboh3_ahb_gate.clk)
+ _REGISTER_CLKDEV("mxc_nand", NULL, &nfc_gate.clk)
+ _REGISTER_CLKDEV("imx-ssi.0", NULL, &ssi1_gate.clk)
+ _REGISTER_CLKDEV("imx-ssi.1", NULL, &ssi2_gate.clk)
+ _REGISTER_CLKDEV("imx-ssi.2", NULL, &ssi3_gate.clk)
+ _REGISTER_CLKDEV("imx-sdma", NULL, &sdma_gate.clk)
+ _REGISTER_CLKDEV("imx51-ecspi.0", NULL, &ecspi1_per_gate.clk)
+ _REGISTER_CLKDEV("imx51-ecspi.1", NULL, &ecspi2_per_gate.clk)
+ _REGISTER_CLKDEV("imx51-cspi.0", NULL, &cspi_ipg_gate.clk)
+ _REGISTER_CLKDEV(NULL, "cpu", &cpu_podf.clk)
+ _REGISTER_CLKDEV(NULL, "iim", &iim_gate.clk)
+ _REGISTER_CLKDEV("sdhci-esdhc-imx.0", NULL, &esdhc1_per_gate.clk)
+ _REGISTER_CLKDEV("sdhci-esdhc-imx.1", NULL, &esdhc2_per_gate.clk)
+ _REGISTER_CLKDEV("sdhci-esdhc-imx.2", NULL, &esdhc3_per_gate.clk)
+ _REGISTER_CLKDEV("sdhci-esdhc-imx.3", NULL, &esdhc4_per_gate.clk)
+ _REGISTER_CLKDEV("imx-ipuv3", NULL, &ipu_gate.clk)
+ _REGISTER_CLKDEV("imx-ipuv3", "di0", &ipu_di0_gate.clk)
+ _REGISTER_CLKDEV("imx-ipuv3", "di1", &ipu_di1_gate.clk)
+ _REGISTER_CLKDEV("imx2-wdt.0", NULL, &dummy.clk)
+ _REGISTER_CLKDEV("imx2-wdt.1", NULL, &dummy.clk)
+ _REGISTER_CLKDEV("imx-keypad", NULL, &dummy.clk)
+};
+
+static struct clk_lookup mx51_lookups[] = {
+ _REGISTER_CLKDEV("imx-i2c.2", NULL, &hsi2c_gate.clk)
+ _REGISTER_CLKDEV("imx27-fec.0", NULL, &fec_gate.clk)
+ _REGISTER_CLKDEV(NULL, "mipi_hsp", &mx51_mipi_hsp_gate.clk)
+};
+
+static struct clk_lookup mx53_lookups[] = {
+ _REGISTER_CLKDEV("imx25-fec.0", NULL, &fec_gate.clk)
+};
+
+struct clk *mx5_on_clocks[] = {
+ &uart1_ipg_gate.clk,
+ &uart2_ipg_gate.clk,
+ &uart3_ipg_gate.clk,
+ &gpt_ipg_gate.clk,
+ &esdhc1_ipg_gate.clk,
+ &esdhc2_ipg_gate.clk,
+ &esdhc3_ipg_gate.clk,
+ &esdhc4_ipg_gate.clk,
+ &ecspi1_ipg_gate.clk,
+ &ecspi2_ipg_gate.clk,
+ &cspi_ipg_gate.clk,
+};
+
+/*
+ * TODO: macro help limit the effect of clk api change.
+ * May be removed finally.
+ */
+#define _REGISTER_CLK(_clk, _ops, _flags) \
+ &(_clk).clk,
+
+struct clk *mx5_clk_array[] = {
+ _REGISTER_CLK(ckil, &clk_fixed_ops, CLK_IS_ROOT)
+ _REGISTER_CLK(osc, &clk_fixed_ops, CLK_IS_ROOT)
+ _REGISTER_CLK(ckih1, &clk_fixed_ops, CLK_IS_ROOT)
+ _REGISTER_CLK(ckih2, &clk_fixed_ops, CLK_IS_ROOT)
+ _REGISTER_CLK(pll1, &clk_pllv2_ops, 0)
+ _REGISTER_CLK(pll2, &clk_pllv2_ops, 0)
+ _REGISTER_CLK(pll3, &clk_pllv2_ops, 0)
+ /*
+ * pll4 is only used by mx53. we put it here because
+ * tve_ext_sel use it early
+ */
+ _REGISTER_CLK(pll4, &clk_pllv2_ops, 0)
+ _REGISTER_CLK(pll4_sw, &clk_mux_ops, 0)
+ _REGISTER_CLK(dummy, &clk_dummy_ops, CLK_IS_ROOT)
+ _REGISTER_CLK(lp_apm, &clk_mux_ops, 0)
+ _REGISTER_CLK(step_pll2_div, &clk_divider_ops, 0)
+ _REGISTER_CLK(step_pll3_div, &clk_divider_ops, 0)
+ _REGISTER_CLK(step_clk, &clk_mux_ops, 0)
+ _REGISTER_CLK(pll1_sw, &clk_mux_ops, 0)
+ _REGISTER_CLK(pll2_sw, &clk_mux_ops, 0)
+ _REGISTER_CLK(pll3_sw, &clk_mux_ops, 0)
+ _REGISTER_CLK(periph_apm, &clk_mux_ops, 0)
+ _REGISTER_CLK(main_bus, &clk_mux_ops, 0)
+ _REGISTER_CLK(ahb_root, &clk_divider_ops, 0)
+ _REGISTER_CLK(ipg, &clk_divider_ops, 0)
+ _REGISTER_CLK(perclk_lp_apm, &clk_mux_ops, 0)
+ _REGISTER_CLK(perclk_pred1, &clk_divider_ops, 0)
+ _REGISTER_CLK(perclk_pred2, &clk_divider_ops, 0)
+ _REGISTER_CLK(perclk_podf, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
+ _REGISTER_CLK(ipg_perclk, &clk_mux_ops, 0)
+ _REGISTER_CLK(axi_a, &clk_divider_ops, 0)
+ _REGISTER_CLK(axi_b, &clk_divider_ops, 0)
+ _REGISTER_CLK(gpu2d, &clk_mux_ops, 0)
+ _REGISTER_CLK(arm_axi, &clk_mux_ops, 0)
+ _REGISTER_CLK(ipu_hsp, &clk_mux_ops, 0)
+ _REGISTER_CLK(gpu, &clk_mux_ops, 0)
+ _REGISTER_CLK(vpu_axi_root, &clk_mux_ops, 0)
+ _REGISTER_CLK(ddr_root, &clk_mux_ops, 0)
+ _REGISTER_CLK(uart_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(uart_pred, &clk_divider_ops, 0)
+ _REGISTER_CLK(uart_root, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
+ _REGISTER_CLK(esdhc1_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(esdhc1_pred, &clk_divider_ops, 0)
+ _REGISTER_CLK(esdhc1_podf, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
+ _REGISTER_CLK(esdhc2_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(esdhc2_pred, &clk_divider_ops, 0)
+ _REGISTER_CLK(esdhc2_podf, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
+ _REGISTER_CLK(esdhc3_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(esdhc4_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(emi_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(emi_slow_podf, &clk_divider_ops, 0)
+ _REGISTER_CLK(nfc_podf, &clk_divider_ops, 0)
+ _REGISTER_CLK(ssi_lp_apm, &clk_mux_ops, 0)
+ _REGISTER_CLK(ssi1_clk_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(ssi1_clk_pred, &clk_divider_ops, 0)
+ _REGISTER_CLK(ssi1_clk, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
+ _REGISTER_CLK(ssi2_clk_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(ssi2_clk_pred, &clk_divider_ops, 0)
+ _REGISTER_CLK(ssi2_clk, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
+ _REGISTER_CLK(ssi3_clk, &clk_mux_ops, 0)
+ _REGISTER_CLK(ecspi_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(ecspi_pred, &clk_divider_ops, 0)
+ _REGISTER_CLK(ecspi_podf, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
+ _REGISTER_CLK(usboh3_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(usboh3_pred, &clk_divider_ops, 0)
+ _REGISTER_CLK(usboh3_podf, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
+ _REGISTER_CLK(usb_phy_pred, &clk_divider_ops, 0)
+ _REGISTER_CLK(usb_phy_podf, &clk_divider_ops, HINT_PARENT_RATE_CHANGE)
+ _REGISTER_CLK(usb_phy_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(cpu_podf, &clk_divider_ops, 0)
+ _REGISTER_CLK(ipu_di0_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(ipu_di1_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(tve_ext_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(tve_pred, &clk_divider_ops, 0)
+ _REGISTER_CLK(tve_sel, &clk_mux_ops, 0)
+ _REGISTER_CLK(ahbmux1, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(aips_tz1, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(aips_tz2, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ahb_max, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(iim_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(uart1_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(uart1_per_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(uart2_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(uart2_per_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(uart3_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(uart3_per_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(i2c1_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(i2c2_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(gpt_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(pwm1_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(pwm1_hf_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(pwm2_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(pwm2_hf_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(gpt_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(fec_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(usboh3_ahb_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(usboh3_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(tve_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(esdhc1_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(esdhc1_per_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(esdhc2_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(esdhc2_per_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(esdhc3_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(esdhc3_per_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(esdhc4_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(esdhc4_per_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ssi1_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ssi1_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ssi2_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ssi2_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ssi3_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ssi3_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ecspi1_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ecspi1_per_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ecspi2_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ecspi2_per_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(cspi_ipg_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(sdma_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ipu_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(emi_fast_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(emi_slow_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(nfc_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ipu_di0_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(ipu_di1_gate, &clk_gate2b_ops, 0)
+};
+
+struct clk *mx51_clk_array[] = {
+ _REGISTER_CLK(ddr_hf_mx51, &clk_divider_ops, 0)
+ _REGISTER_CLK(ddr_root_mx51, &clk_mux_ops, 0)
+ _REGISTER_CLK(hsi2c_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(mx51_usb_phy_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(mx51_mipi_hsc1_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(mx51_mipi_hsc2_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(mx51_mipi_esc_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(mx51_mipi_hsp_gate, &clk_gate2b_ops, 0)
+};
+
+struct clk *mx53_clk_array[] = {
+ _REGISTER_CLK(mx53_usb_phy1_gate, &clk_gate2b_ops, 0)
+ _REGISTER_CLK(mx53_usb_phy2_gate, &clk_gate2b_ops, 0)
+};
+
+static void clk_register_array(struct clk **clks, int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ clk_init(NULL, clks[i]);
+}
+
+static void clkdev_add_array(struct clk_lookup *lookup, int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ clkdev_add(&lookup[i]);
+}
+
+static void mx5_clocks_common_init(unsigned long rate_ckil, unsigned long rate_osc,
+ unsigned long rate_ckih1, unsigned long rate_ckih2)
+{
+ int i;
+
+ ckil.fixed_rate = rate_ckil;
+ osc.fixed_rate = rate_osc;
+ ckih1.fixed_rate = rate_ckih1;
+ ckih2.fixed_rate = rate_ckih2;
+
+ clk_register_array(mx5_clk_array, ARRAY_SIZE(mx5_clk_array));
+ clkdev_add_array(mx5_lookups, ARRAY_SIZE(mx5_lookups));
+
+ /* Set SDHC parents to be PLL2 */
+ clk_set_parent(&esdhc1_sel.clk, &pll2_sw.clk);
+ clk_set_parent(&esdhc2_sel.clk, &pll2_sw.clk);
+
+ /* keep device ipg clocks on until drivers handle it */
+ for (i = 0; i < ARRAY_SIZE(mx5_on_clocks); i++) {
+ clk_prepare(mx5_on_clocks[i]);
+ clk_enable(mx5_on_clocks[i]);
+ }
+}
+
+int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
+ unsigned long rate_ckih1, unsigned long rate_ckih2)
+{
+ /* Clock tree has i.MX51 layout. i.MX53 needs some fixups */
+ pll1.base = MX53_DPLL1_BASE;
+ pll2.base = MX53_DPLL2_BASE;
+ pll3.base = MX53_DPLL3_BASE;
+ esdhc3_per_gate.clk.parent = &esdhc2_podf.clk;
+ esdhc2_per_gate.clk.parent = &esdhc3_sel.clk;
+ tve_gate.clk.parent = &tve_pred.clk;
+ tve_pred.clk.parent = &tve_ext_sel.clk;
+ tve_ext_sel_clks[0] = &pll4_sw.clk;
+ tve_ext_sel_clks[1] = &ckih1.clk;
+
+ mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
+ clk_register_array(mx53_clk_array, ARRAY_SIZE(mx53_clk_array));
+ clkdev_add_array(mx53_lookups, ARRAY_SIZE(mx53_lookups));
+
+ /* set SDHC root clock to 200MHZ*/
+ clk_set_rate(&esdhc1_podf.clk, 200000000);
+ clk_set_rate(&esdhc2_podf.clk, 200000000);
+
+ /* System timer */
+ mxc_timer_init(&gpt_gate.clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
+ MX53_INT_GPT);
+
+ clk_prepare(&iim_gate.clk);
+ clk_enable(&iim_gate.clk);
+ imx_print_silicon_rev("i.MX53", mx53_revision());
+ clk_disable(&iim_gate.clk);
+ clk_unprepare(&iim_gate.clk);
+
+ return 0;
+}
+
+int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
+ unsigned long rate_ckih1, unsigned long rate_ckih2)
+{
+ mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
+ clk_register_array(mx51_clk_array, ARRAY_SIZE(mx5_clk_array));
+ clkdev_add_array(mx51_lookups, ARRAY_SIZE(mx51_lookups));
+
+ /* set SDHC root clock to 166.25MHZ*/
+ clk_set_rate(&esdhc1_podf.clk, 166250000);
+ clk_set_rate(&esdhc2_podf.clk, 166250000);
+
+ /* System timer */
+ mxc_timer_init(&gpt_gate.clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
+ MX51_INT_GPT);
+
+ clk_prepare(&iim_gate.clk);
+ clk_enable(&iim_gate.clk);
+ imx_print_silicon_rev("i.MX51", mx51_revision());
+ clk_disable(&iim_gate.clk);
+
+ return 0;
+}