@@ -24,6 +24,8 @@
#define DEFAULT_WIN 0
+#define EXYNOS_DRM_PITCH_ALIGN 8
+
#define to_exynos_crtc(x) container_of(x, struct exynos_drm_crtc, base)
#define to_exynos_plane(x) container_of(x, struct exynos_drm_plane, base)
@@ -417,7 +417,7 @@ int exynos_drm_gem_dumb_create(struct drm_file *file_priv,
* with DRM_IOCTL_MODE_CREATE_DUMB command.
*/
- args->pitch = args->width * ((args->bpp + 7) / 8);
+ args->pitch = roundup(args->width, EXYNOS_DRM_PITCH_ALIGN) * ((args->bpp + 7) / 8);
args->size = args->pitch * args->height;
if (is_drm_iommu_supported(dev))
This patch forces all GEM buffers to have pitch aligned at least to 8 pixels. This is a common requirement for various Exynos IPP blocks, which otherwise won't be able to operate on buffers of random size. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> --- drivers/gpu/drm/exynos/exynos_drm_drv.h | 2 ++ drivers/gpu/drm/exynos/exynos_drm_gem.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-)