diff mbox series

pinctrl: sunxi: sunxi_pconf_set: use correct offset

Message ID 20220525190423.410609-1-andrey.lalaev@gmail.com
State Accepted
Commit cd4c1e65a32afd003b08ad4aafe1e4d3e4e8e61b
Headers show
Series pinctrl: sunxi: sunxi_pconf_set: use correct offset | expand

Commit Message

Andrei Lalaev May 25, 2022, 7:04 p.m. UTC
Some Allwinner SoCs have 2 pinctrls (PIO and R_PIO).
Previous implementation used absolute pin numbering and it was incorrect
for R_PIO pinctrl.
It's necessary to take into account the base pin number.

Fixes: 90be64e27621 ("pinctrl: sunxi: implement pin_config_set")
Signed-off-by: Andrei Lalaev <andrey.lalaev@gmail.com>
---
 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Jernej Škrabec May 26, 2022, 8:52 p.m. UTC | #1
Hi!

Dne sreda, 25. maj 2022 ob 21:04:25 CEST je Andrei Lalaev napisal(a):
> Some Allwinner SoCs have 2 pinctrls (PIO and R_PIO).
> Previous implementation used absolute pin numbering and it was incorrect
> for R_PIO pinctrl.
> It's necessary to take into account the base pin number.

You didn't explain how issue manifests. How did you find it?

Best regards,
Jernej

> 
> Fixes: 90be64e27621 ("pinctrl: sunxi: implement pin_config_set")
> Signed-off-by: Andrei Lalaev <andrey.lalaev@gmail.com>
> ---
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/
pinctrl-sunxi.c
> index d9327d7d56ee..dd928402af99 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -544,6 +544,8 @@ static int sunxi_pconf_set(struct pinctrl_dev *pctldev, 
unsigned pin,
>  	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
>  	int i;
>  
> +	pin -= pctl->desc->pin_base;
> +
>  	for (i = 0; i < num_configs; i++) {
>  		enum pin_config_param param;
>  		unsigned long flags;
> -- 
> 2.25.1
> 
>
Jernej Škrabec June 15, 2022, 3:56 p.m. UTC | #2
Dne sreda, 15. junij 2022 ob 15:17:55 CEST je Linus Walleij napisal(a):
> On Wed, May 25, 2022 at 9:08 PM Andrei Lalaev <andrey.lalaev@gmail.com> 
wrote:
> 
> > Some Allwinner SoCs have 2 pinctrls (PIO and R_PIO).
> > Previous implementation used absolute pin numbering and it was incorrect
> > for R_PIO pinctrl.
> > It's necessary to take into account the base pin number.
> >
> > Fixes: 90be64e27621 ("pinctrl: sunxi: implement pin_config_set")
> > Signed-off-by: Andrei Lalaev <andrey.lalaev@gmail.com>
> 
> It fixes a patch by Maxime so want Maxime to ACK this if it should be
> applied. Paging Andre and Yangtao too, would be sad if we don't apply it
> if it is a necessary fix.
Andrei Lalaev June 15, 2022, 6:06 p.m. UTC | #3
Hi!

Jernej, sorry to have kept you waiting.

On Wed, May 26, 2022 at 11:52 PM Jernej Škrabec <jernej.skrabec@gmail.com> wrote:
> You didn't explain how issue manifests. How did you find it?

I noticed this problem when tried to pull-down a pin at kernel 5.3.11.

sunxi_pconf_set uses sunxi_pconf_reg to get offset and shift.
sunxi_pconf_reg uses the next functions to calculate register offset:
	sunxi_dlevel_reg
	sunxi_dlevel_offset
	sunxi_pull_reg
	sunxi_pull_offset

These functions calculate the offset relative to the pinctrl address.
Let's consider the sunxi_pconf_reg's output with the following arguments:
	pin = 354 (PL2)
	param = PIN_CONFIG_BIAS_PULL_UP

	So the sunxi_pull_reg is called and it returns "0x1a8".
	This value too high to be register offset :)

But with my patch:
	pin_base = 352
	pin = 354 - 352 = 2 (PL2)
	param = PIN_CONFIG_BIAS_PULL_UP

	And sunxi_pull_reg returns "0x1c" as expected.
	According to the datasheet [1] (page 349) it's the PL_PULL register.

P.S. sunxi_pconf_get calculates the pin number in the same way (line 490).

---
[1] https://linux-sunxi.org/images/4/4b/Allwinner_H3_Datasheet_V1.2.pdf

Best regards,
Andrei Lalaev
Samuel Holland June 17, 2022, 4:32 a.m. UTC | #4
On 6/15/22 10:56 AM, Jernej Škrabec wrote:
> Dne sreda, 15. junij 2022 ob 15:17:55 CEST je Linus Walleij napisal(a):
>> On Wed, May 25, 2022 at 9:08 PM Andrei Lalaev <andrey.lalaev@gmail.com> 
> wrote:
>>
>>> Some Allwinner SoCs have 2 pinctrls (PIO and R_PIO).
>>> Previous implementation used absolute pin numbering and it was incorrect
>>> for R_PIO pinctrl.
>>> It's necessary to take into account the base pin number.
>>>
>>> Fixes: 90be64e27621 ("pinctrl: sunxi: implement pin_config_set")
>>> Signed-off-by: Andrei Lalaev <andrey.lalaev@gmail.com>
>>
>> It fixes a patch by Maxime so want Maxime to ACK this if it should be
>> applied. Paging Andre and Yangtao too, would be sad if we don't apply it
>> if it is a necessary fix.
> 
> From what I can see, this fixes makes code consistent with pattern in other 
> functions, so I think it's good.

Reviewed-by: Samuel Holland <samuel@sholland.org>

This patch looks right to me as well. It appears the subtraction was
accidentally removed in the referenced commit.

Regards,
Samuel
diff mbox series

Patch

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index d9327d7d56ee..dd928402af99 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -544,6 +544,8 @@  static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 	int i;
 
+	pin -= pctl->desc->pin_base;
+
 	for (i = 0; i < num_configs; i++) {
 		enum pin_config_param param;
 		unsigned long flags;