| Message ID | 1654130923-18722-1-git-send-email-quic_sibis@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/3] dt-bindings: interconnect: Update email address | expand |
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 116e434d0daa..bf538c0c5a81 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider maintainers: - - Sibi Sankar <sibis@codeaurora.org> + - Sibi Sankar <quic_sibis@quicinc.com> description: L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
Update email address to the quicinc.com domain. Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)