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[PULL,54/55] target/arm: Add isar_feature_aa64_sme

Message ID 20220609090537.1971756-55-peter.maydell@linaro.org
State Accepted
Commit f305bf9436896b4cd9ef622034e166b024780874
Headers show
Series [PULL,01/55] target/arm: Declare support for FEAT_RASv1p1 | expand

Commit Message

Peter Maydell June 9, 2022, 9:05 a.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>

This will be used for implementing FEAT_SME.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 5 +++++
 1 file changed, 5 insertions(+)
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Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e45b5cb7fe1..2e6153c5409 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4048,6 +4048,11 @@  static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
 }
 
+static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
+}
+
 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&