@@ -86,112 +86,7 @@ static struct freq_tbl clk_tbl_aif_osr_393[] = {
{ }
};
-static struct clk_rcg mi2s_osr_src = {
- .ns_reg = 0x48,
- .md_reg = 0x4c,
- .mn = {
- .mnctr_en_bit = 8,
- .mnctr_reset_bit = 7,
- .mnctr_mode_shift = 5,
- .n_val_shift = 24,
- .m_val_shift = 8,
- .width = 8,
- },
- .p = {
- .pre_div_shift = 3,
- .pre_div_width = 2,
- },
- .s = {
- .src_sel_shift = 0,
- .parent_map = lcc_pxo_pll4_map,
- },
- .freq_tbl = clk_tbl_aif_osr_393,
- .clkr = {
- .enable_reg = 0x48,
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_osr_src",
- .parent_names = lcc_pxo_pll4,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
- },
-};
-
-static const char * const lcc_mi2s_parents[] = {
- "mi2s_osr_src",
-};
-
-static struct clk_branch mi2s_osr_clk = {
- .halt_reg = 0x50,
- .halt_bit = 1,
- .halt_check = BRANCH_HALT_ENABLE,
- .clkr = {
- .enable_reg = 0x48,
- .enable_mask = BIT(17),
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_osr_clk",
- .parent_names = lcc_mi2s_parents,
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- },
-};
-
-static struct clk_regmap_div mi2s_div_clk = {
- .reg = 0x48,
- .shift = 10,
- .width = 4,
- .clkr = {
- .enable_reg = 0x48,
- .enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_div_clk",
- .parent_names = lcc_mi2s_parents,
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- },
- },
-};
-
-static struct clk_branch mi2s_bit_div_clk = {
- .halt_reg = 0x50,
- .halt_bit = 0,
- .halt_check = BRANCH_HALT_ENABLE,
- .clkr = {
- .enable_reg = 0x48,
- .enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_bit_div_clk",
- .parent_names = (const char *[]){ "mi2s_div_clk" },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- },
-};
-
-static struct clk_regmap_mux mi2s_bit_clk = {
- .reg = 0x48,
- .shift = 14,
- .width = 1,
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_bit_clk",
- .parent_names = (const char *[]){
- "mi2s_bit_div_clk",
- "mi2s_codec_clk",
- },
- .num_parents = 2,
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- },
-};
-
-#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
+#define CLK_AIF_OSR_SRC(prefix, _ns, _md) \
static struct clk_rcg prefix##_osr_src = { \
.ns_reg = _ns, \
.md_reg = _md, \
@@ -228,14 +123,15 @@ static struct clk_rcg prefix##_osr_src = { \
static const char * const lcc_##prefix##_parents[] = { \
#prefix "_osr_src", \
}; \
- \
+
+#define CLK_AIF_OSR_CLK(prefix, _ns, hr, en_bit) \
static struct clk_branch prefix##_osr_clk = { \
.halt_reg = hr, \
.halt_bit = 1, \
.halt_check = BRANCH_HALT_ENABLE, \
.clkr = { \
.enable_reg = _ns, \
- .enable_mask = BIT(21), \
+ .enable_mask = BIT(en_bit), \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_osr_clk", \
.parent_names = lcc_##prefix##_parents, \
@@ -245,11 +141,12 @@ static struct clk_branch prefix##_osr_clk = { \
}, \
}, \
}; \
- \
+
+#define CLK_AIF_OSR_DIV_CLK(prefix, _ns, _width) \
static struct clk_regmap_div prefix##_div_clk = { \
.reg = _ns, \
.shift = 10, \
- .width = 8, \
+ .width = _width, \
.clkr = { \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_div_clk", \
@@ -259,14 +156,15 @@ static struct clk_regmap_div prefix##_div_clk = { \
}, \
}, \
}; \
- \
+
+#define CLK_AIF_OSR_BIT_DIV_CLK(prefix, _ns, hr, en_bit) \
static struct clk_branch prefix##_bit_div_clk = { \
.halt_reg = hr, \
.halt_bit = 0, \
.halt_check = BRANCH_HALT_ENABLE, \
.clkr = { \
.enable_reg = _ns, \
- .enable_mask = BIT(19), \
+ .enable_mask = BIT(en_bit), \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_bit_div_clk", \
.parent_names = (const char *[]){ \
@@ -278,10 +176,11 @@ static struct clk_branch prefix##_bit_div_clk = { \
}, \
}, \
}; \
- \
+
+#define CLK_AIF_OSR_BIT_CLK(prefix, _ns, _shift) \
static struct clk_regmap_mux prefix##_bit_clk = { \
.reg = _ns, \
- .shift = 18, \
+ .shift = _shift, \
.width = 1, \
.clkr = { \
.hw.init = &(struct clk_init_data){ \
@@ -295,7 +194,20 @@ static struct clk_regmap_mux prefix##_bit_clk = { \
.flags = CLK_SET_RATE_PARENT, \
}, \
}, \
-}
+};
+
+CLK_AIF_OSR_SRC(mi2s, 0x48, 0x4c)
+CLK_AIF_OSR_CLK(mi2s, 0x48, 0x50, 17)
+CLK_AIF_OSR_DIV_CLK(mi2s, 0x48, 4)
+CLK_AIF_OSR_BIT_DIV_CLK(mi2s, 0x48, 0x50, 15)
+CLK_AIF_OSR_BIT_CLK(mi2s, 0x48, 14)
+
+#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
+ CLK_AIF_OSR_SRC(prefix, _ns, _md) \
+ CLK_AIF_OSR_CLK(prefix, _ns, hr, 21) \
+ CLK_AIF_OSR_DIV_CLK(prefix, _ns, 8) \
+ CLK_AIF_OSR_BIT_DIV_CLK(prefix, _ns, hr, 19) \
+ CLK_AIF_OSR_BIT_CLK(prefix, _ns, 18)
CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
Split and extend existing CLK_AIF_OSR_DIV macro to implement mi2s clocks. This simplifies the driver and removes extra code duplication. The clock mi2s_div_clk used .enable_reg/.enable_bit, however these fields are not used with by the clk_regmap_div_ops, thus they are silently dropped. Clock enablement is handled in the mi2s_bit_div_clk clock. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/lcc-msm8960.c | 142 +++++++-------------------------- 1 file changed, 27 insertions(+), 115 deletions(-)