| Message ID | 20220628042117.368549-15-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Scalable Matrix Extension | expand |
On Tue, 28 Jun 2022 at 05:49, Richard Henderson <richard.henderson@linaro.org> wrote: > > Mark these as a non-streaming instructions, which should trap > if full a64 support is not enabled in streaming mode. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/sme-fa64.decode | 3 --- > target/arm/translate-sve.c | 2 ++ > 2 files changed, 2 insertions(+), 3 deletions(-) > > diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode > index 7a0b05cf2c..33bbd13bcb 100644 > --- a/target/arm/sme-fa64.decode > +++ b/target/arm/sme-fa64.decode > @@ -57,6 +57,3 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e > # --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm) > # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) > # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) > - > -FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) > -FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) > diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c > index 11874a8e77..e5e9e1e0ca 100644 > --- a/target/arm/translate-sve.c > +++ b/target/arm/translate-sve.c > @@ -5062,6 +5062,7 @@ static bool trans_LD1RO_zprr(DisasContext *s, arg_rprr_load *a) > if (a->rm == 31) { > return false; > } > + s->is_nonstreaming = true; > if (sve_access_check(s)) { > TCGv_i64 addr = new_tmp_a64(s); > tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); > @@ -5076,6 +5077,7 @@ static bool trans_LD1RO_zpri(DisasContext *s, arg_rpri_load *a) > if (!dc_isar_feature(aa64_sve_f64mm, s)) { > return false; > } > + s->is_nonstreaming = true; > if (sve_access_check(s)) { > TCGv_i64 addr = new_tmp_a64(s); > tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32); The sve.decode lines for these two trans functions: LD1RO_zprr 1010010 .. 01 ..... 000 ... ..... ..... \ @rprr_load_msz nreg=0 LD1RO_zpri 1010010 .. 01 0.... 001 ... ..... ..... \ @rpri_load_msz nreg=0 don't match up with the FAIL line. The FAIL lines correspond to unallocated encodings in the decode tables in the main Arm ARM so we can assume this is an error in the SME supplement. We should use the right encoding lines in the original commit of sme-fa64.decode and mention that in its commit message. They should I believe be: FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) (differences only in bits [22:21]). For this patch, Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 7a0b05cf2c..33bbd13bcb 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -57,6 +57,3 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e # --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm) # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) - -FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) -FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 11874a8e77..e5e9e1e0ca 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5062,6 +5062,7 @@ static bool trans_LD1RO_zprr(DisasContext *s, arg_rprr_load *a) if (a->rm == 31) { return false; } + s->is_nonstreaming = true; if (sve_access_check(s)) { TCGv_i64 addr = new_tmp_a64(s); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); @@ -5076,6 +5077,7 @@ static bool trans_LD1RO_zpri(DisasContext *s, arg_rpri_load *a) if (!dc_isar_feature(aa64_sve_f64mm, s)) { return false; } + s->is_nonstreaming = true; if (sve_access_check(s)) { TCGv_i64 addr = new_tmp_a64(s); tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32);
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-)