diff mbox series

[08/13] ARM: dts: qcom: fix dtc warning for missing #address-cells for ipq8064

Message ID 20220705133917.8405-9-ansuelsmth@gmail.com
State New
Headers show
Series Add ipq806x missing bindings | expand

Commit Message

Christian Marangi July 5, 2022, 1:39 p.m. UTC 
Fix dtc warning for missing #address-cells for ipq8064.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 ++
 1 file changed, 2 insertions(+)

Comments

Krzysztof Kozlowski July 6, 2022, 8:37 a.m. UTC | #1 
On 05/07/2022 15:39, Christian Marangi wrote:
> Fix dtc warning for missing #address-cells for ipq8064.

Paste the applicable part of warning in the commit log.

> 


Best regards,
Krzysztof
Christian Marangi July 6, 2022, 10:12 a.m. UTC | #2 
On Wed, Jul 06, 2022 at 10:37:47AM +0200, Krzysztof Kozlowski wrote:
> On 05/07/2022 15:39, Christian Marangi wrote:
> > Fix dtc warning for missing #address-cells for ipq8064.
> 
> Paste the applicable part of warning in the commit log.
> 
> > 
> 
> 
> Best regards,
> Krzysztof

Can I squash here the warning from the smb patch?
Krzysztof Kozlowski July 6, 2022, 2:45 p.m. UTC | #3 
On 06/07/2022 12:12, Christian Marangi wrote:
> On Wed, Jul 06, 2022 at 10:37:47AM +0200, Krzysztof Kozlowski wrote:
>> On 05/07/2022 15:39, Christian Marangi wrote:
>>> Fix dtc warning for missing #address-cells for ipq8064.
>>
>> Paste the applicable part of warning in the commit log.
>>
>>>
>>
>>
>> Best regards,
>> Krzysztof
> 
> Can I squash here the warning from the smb patch?

Do you fix the same stuff in both commits?

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index e13f6ae92e05..b5aede3d7ccf 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -352,6 +352,7 @@  qcom_pinmux: pinmux@800000 {
 			gpio-ranges = <&qcom_pinmux 0 0 69>;
 			#gpio-cells = <2>;
 			interrupt-controller;
+			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -473,6 +474,7 @@  mux {
 		intc: interrupt-controller@2000000 {
 			compatible = "qcom,msm-qgic2";
 			interrupt-controller;
+			#address-cells = <0>;
 			#interrupt-cells = <3>;
 			reg = <0x02000000 0x1000>,
 			      <0x02002000 0x1000>;