| Message ID | 20220707173733.404947-2-robimarko@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v6,1/4] mailbox: qcom-apcs-ipc: make regmap max_register configurable | expand |
On Thu 07 Jul 12:37 CDT 2022, Robert Marko wrote: > IPQ8074 has the APSS clock controller utilizing the same register space as > the APCS, so provide access to the APSS utilizing a child device like > IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS > clock driver. > > Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn > --- > Changes in v6: > * Adjust max_register value using match data instead of globally > > Changes in v5: > * Use lower case hex for max_register > * Update the APSS clock name to match the new one without commas > --- > drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c > index c05f3276d02c..5d6b41fa6256 100644 > --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c > +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c > @@ -34,6 +34,12 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = { > .offset = 8, .clk_name = "qcom,apss-ipq6018-clk" > }; > > +static const struct qcom_apcs_ipc_data ipq8074_apcs_data = { > + .offset = 8, > + .max_register = 0x5ffc, > + .clk_name = "qcom-apss-ipq8074-clk" > +}; > + > static const struct qcom_apcs_ipc_data msm8916_apcs_data = { > .offset = 8, .clk_name = "qcom-apcs-msm8916-clk" > }; > @@ -148,7 +154,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev) > /* .data is the offset of the ipc register within the global block */ > static const struct of_device_id qcom_apcs_ipc_of_match[] = { > { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data }, > - { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data }, > + { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data }, > { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data }, > { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data }, > { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data }, > -- > 2.36.1 >
On Wed, 13 Jul 2022 at 22:44, Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > > On Thu 07 Jul 12:37 CDT 2022, Robert Marko wrote: > > > IPQ8074 has the APSS clock controller utilizing the same register space as > > the APCS, so provide access to the APSS utilizing a child device like > > IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS > > clock driver. > > > > Signed-off-by: Robert Marko <robimarko@gmail.com> > > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Bjorn, please ignore the v6 series, a way simplified and better support is in the v8 series. Which is mostly reviewed, only DTS is pending. Regards, Robert > > Regards, > Bjorn > > > --- > > Changes in v6: > > * Adjust max_register value using match data instead of globally > > > > Changes in v5: > > * Use lower case hex for max_register > > * Update the APSS clock name to match the new one without commas > > --- > > drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 +++++++- > > 1 file changed, 7 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c > > index c05f3276d02c..5d6b41fa6256 100644 > > --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c > > +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c > > @@ -34,6 +34,12 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = { > > .offset = 8, .clk_name = "qcom,apss-ipq6018-clk" > > }; > > > > +static const struct qcom_apcs_ipc_data ipq8074_apcs_data = { > > + .offset = 8, > > + .max_register = 0x5ffc, > > + .clk_name = "qcom-apss-ipq8074-clk" > > +}; > > + > > static const struct qcom_apcs_ipc_data msm8916_apcs_data = { > > .offset = 8, .clk_name = "qcom-apcs-msm8916-clk" > > }; > > @@ -148,7 +154,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev) > > /* .data is the offset of the ipc register within the global block */ > > static const struct of_device_id qcom_apcs_ipc_of_match[] = { > > { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data }, > > - { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data }, > > + { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data }, > > { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data }, > > { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data }, > > { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data }, > > -- > > 2.36.1 > >
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index c05f3276d02c..5d6b41fa6256 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -34,6 +34,12 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = { .offset = 8, .clk_name = "qcom,apss-ipq6018-clk" }; +static const struct qcom_apcs_ipc_data ipq8074_apcs_data = { + .offset = 8, + .max_register = 0x5ffc, + .clk_name = "qcom-apss-ipq8074-clk" +}; + static const struct qcom_apcs_ipc_data msm8916_apcs_data = { .offset = 8, .clk_name = "qcom-apcs-msm8916-clk" }; @@ -148,7 +154,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev) /* .data is the offset of the ipc register within the global block */ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data }, - { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data }, + { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data }, { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data }, { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data }, { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data },
IPQ8074 has the APSS clock controller utilizing the same register space as the APCS, so provide access to the APSS utilizing a child device like IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS clock driver. Signed-off-by: Robert Marko <robimarko@gmail.com> --- Changes in v6: * Adjust max_register value using match data instead of globally Changes in v5: * Use lower case hex for max_register * Update the APSS clock name to match the new one without commas --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)