| Message ID | 20220707170129.217086-1-Perry.Yuan@amd.com |
|---|---|
| State | Superseded |
| Headers | show
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From: Perry Yuan <Perry.Yuan@amd.com>
To: <rafael.j.wysocki@intel.com>, <viresh.kumar@linaro.org>,
<Ray.Huang@amd.com>, Huang Rui <ray.huang@amd.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
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<Jinzhou.Su@amd.com>, <Xinmei.Huang@amd.com>,
<Xiaojian.Du@amd.com>, <Li.Meng@amd.com>,
Perry Yuan <Perry.Yuan@amd.com>
Subject: [PATCH 12/12] cpufreq: amd_pstate: update transition delay time to
1ms
Date: Thu, 7 Jul 2022 13:01:29 -0400
Message-ID: <20220707170129.217086-1-Perry.Yuan@amd.com>
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| Series |
[01/12] x86/msr: Add the MSR definition for AMD CPPC hardware control.
|
expand
|
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6d81a9a94dde..f16ad0b108e4 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -42,7 +42,7 @@ #include "amd-pstate-trace.h" #define AMD_PSTATE_TRANSITION_LATENCY 20000 -#define AMD_PSTATE_TRANSITION_DELAY 500 +#define AMD_PSTATE_TRANSITION_DELAY 1000 /* * TODO: We need more time to fine tune processors with shared memory solution
Update transition delay time to 1ms, in the AMD CPU autonomous mode and non-autonomous mode, CPPC firmware will decide frequency at 1ms timescale based on the workload utilization. Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> --- drivers/cpufreq/amd-pstate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)