@@ -1189,11 +1189,15 @@ static void a6xx_dump(struct msm_gpu *gpu)
#define VBIF_RESET_ACK_TIMEOUT 100
#define VBIF_RESET_ACK_MASK 0x00f0
+#define CX_GDSCR_OFFSET 0x106c
+#define CX_GDSC_ON_MASK BIT(31)
+
static void a6xx_recover(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
- int i;
+ int i, ret;
+ u32 val;
adreno_dump_info(gpu);
@@ -1220,6 +1224,13 @@ static void a6xx_recover(struct msm_gpu *gpu)
/* And the final one from recover worker */
pm_runtime_put_sync(&gpu->pdev->dev);
+ if (gpu->gpucc_io) {
+ ret = readl_poll_timeout(gpu->gpucc_io + CX_GDSCR_OFFSET, val,
+ !(val & CX_GDSC_ON_MASK), 100, 500000);
+ if (ret)
+ DRM_DEV_INFO(&gpu->pdev->dev, "cx gdsc didn't collapse\n");
+ }
+
for (i = gpu->active_submits; i > 0; i--)
pm_runtime_get(&gpu->pdev->dev);
@@ -881,6 +881,10 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
goto fail;
}
+ gpu->gpucc_io = msm_ioremap(pdev, "gpucc");
+ if (IS_ERR(gpu->gpucc_io))
+ gpu->gpucc_io = NULL;
+
/* Get Interrupt: */
gpu->irq = platform_get_irq(pdev, 0);
if (gpu->irq < 0) {
@@ -217,6 +217,7 @@ struct msm_gpu {
int global_faults;
void __iomem *mmio;
+ void __iomem *gpucc_io;
int irq;
struct msm_gem_address_space *aspace;
To improve our chance of a successful recovery, we should ensure that cx headswitch collapses. Cx headswitch might be kept enabled through a vote from another driver like iommu or even another hardware subsystem. So, poll the cx gdscr register to ensure that it collapses during recovery. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 ++++++++++++- drivers/gpu/drm/msm/msm_gpu.c | 4 ++++ drivers/gpu/drm/msm/msm_gpu.h | 1 + 3 files changed, 17 insertions(+), 1 deletion(-)