| Message ID | 20220712125922.3461675-3-bryan.odonoghue@linaro.org |
|---|---|
| State | Accepted |
| Commit | 159b2f59d65b4d34e225ef8d96ed290a13610d9c |
| Headers | show |
| Series | clk: qcom: gcc-msm8939: Align clock frequencies with downstream driver | expand |
diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c index 628b476a5468e..6a3e2326c72a3 100644 --- a/drivers/clk/qcom/gcc-msm8939.c +++ b/drivers/clk/qcom/gcc-msm8939.c @@ -1003,6 +1003,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = { F(19200000, P_XO, 1, 0, 0), + F(37500000, P_GPLL0, 1, 3, 64), { } };
Standard CCI bus clock clocks are 19.2 MHz and 37.5 MHz. We already define the 19.2 MHz but are missing the 37.5 MHz. See qcom kernel drivers/clk/qcom/clock-gcc-8936.c::ftbl_gcc_camss_cci_clk[] Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> --- drivers/clk/qcom/gcc-msm8939.c | 1 + 1 file changed, 1 insertion(+)