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[v2,1/2] dt-bindings: serial: pl011: Add 'arm,xlnx-uart'

Message ID 20220720142612.19779-2-shubhrajyoti.datta@xilinx.com
State New
Headers show
Series serial: pl011: Add xilinx uart | expand

Commit Message

Shubhrajyoti Datta July 20, 2022, 2:26 p.m. UTC 
The Xilinx Versal board uses the arm,pl011 ip. However the
axi port that it is connected to has a limitation that it allows
only 32-bit accesses. So to differentiate we add a compatible.

Add support for Uart used in Xilinx Versal SOCs as a platform
device.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
---
 Documentation/devicetree/bindings/serial/pl011.yaml | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)
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Patch

diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml
index d8aed84abcd3..bf094ab93086 100644
--- a/Documentation/devicetree/bindings/serial/pl011.yaml
+++ b/Documentation/devicetree/bindings/serial/pl011.yaml
@@ -24,9 +24,13 @@  select:
 
 properties:
   compatible:
-    items:
-      - const: arm,pl011
-      - const: arm,primecell
+    oneOf:
+      - items:
+          - const: arm,pl011
+          - const: arm,primecell
+      - items:
+          - const: arm,pl011
+          - const: arm,xlnx-uart # xilinx uart as platform device
 
   reg:
     maxItems: 1