| Message ID | 20220723100135.91784-1-konrad.dybcio@somainline.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v3,1/3] clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit | expand |
On 23.07.2022 12:15, Christophe JAILLET wrote: > Le 23/07/2022 à 12:01, Konrad Dybcio a écrit : >> Add support for the global clock controller found on SM6375. >> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> >> --- >> Changes since v2: >> - use parent_hws where applicable >> >> drivers/clk/qcom/Kconfig | 8 + >> drivers/clk/qcom/Makefile | 1 + >> drivers/clk/qcom/gcc-sm6375.c | 3931 +++++++++++++++++++++++++++++++++ >> 3 files changed, 3940 insertions(+) >> create mode 100644 drivers/clk/qcom/gcc-sm6375.c >> >> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >> index 415ae4ffab48..ef81eda01649 100644 >> --- a/drivers/clk/qcom/Kconfig >> +++ b/drivers/clk/qcom/Kconfig >> @@ -672,6 +672,14 @@ config SM_GCC_6350 >> Say Y if you want to use peripheral devices such as UART, >> SPI, I2C, USB, SD/UFS, PCIe etc. >> +config SM_GCC_6375 >> + tristate "SM6350 Global Clock Controller" > > Nit: SM6375? Yes, obviously.. I made a mistake here. Konrad > >> + select QCOM_GDSC >> + help >> + Support for the global clock controller on SM6375 devices. >> + Say Y if you want to use peripheral devices such as UART, >> + SPI, I2C, USB, SD/UFS etc. >> +
On 23/07/2022 12:01, Konrad Dybcio wrote: > Add device tree bindings for global clock controller for SM6375 SoCs. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > --- > Changes since v2: > - reference qcom,gcc.yaml > > .../bindings/clock/qcom,sm6375-gcc.yaml | 48 ++++ > include/dt-bindings/clock/qcom,sm6375-gcc.h | 234 ++++++++++++++++++ > 2 files changed, 282 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml > create mode 100644 include/dt-bindings/clock/qcom,sm6375-gcc.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml > new file mode 100644 > index 000000000000..fb1c36888d18 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml > @@ -0,0 +1,48 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Global Clock & Reset Controller Binding for SM6375 > + > +maintainers: > + - Konrad Dybcio <konrad.dybcio@somainline.org> > + > +description: | > + Qualcomm global clock control module which supports the clocks, resets and > + power domains on SM6375 > + > + See also: > + - dt-bindings/clock/qcom,sm6375-gcc.h > + > +allOf: > + - $ref: qcom,gcc.yaml# > + > +properties: > + compatible: > + const: qcom,sm6375-gcc > + > + clocks: > + items: > + - description: Board XO source > + - description: Board XO Active-Only source > + - description: Sleep clock source What happened to clock-names? > + I would assume these are required for the clock controller... and they were before, so what happened? Best regards, Krzysztof
On 23.07.2022 19:46, Krzysztof Kozlowski wrote: > On 23/07/2022 12:01, Konrad Dybcio wrote: >> Add device tree bindings for global clock controller for SM6375 SoCs. >> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> >> --- >> Changes since v2: >> - reference qcom,gcc.yaml >> >> .../bindings/clock/qcom,sm6375-gcc.yaml | 48 ++++ >> include/dt-bindings/clock/qcom,sm6375-gcc.h | 234 ++++++++++++++++++ >> 2 files changed, 282 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml >> create mode 100644 include/dt-bindings/clock/qcom,sm6375-gcc.h >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml >> new file mode 100644 >> index 000000000000..fb1c36888d18 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml >> @@ -0,0 +1,48 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Global Clock & Reset Controller Binding for SM6375 >> + >> +maintainers: >> + - Konrad Dybcio <konrad.dybcio@somainline.org> >> + >> +description: | >> + Qualcomm global clock control module which supports the clocks, resets and >> + power domains on SM6375 >> + >> + See also: >> + - dt-bindings/clock/qcom,sm6375-gcc.h >> + >> +allOf: >> + - $ref: qcom,gcc.yaml# >> + >> +properties: >> + compatible: >> + const: qcom,sm6375-gcc >> + >> + clocks: >> + items: >> + - description: Board XO source >> + - description: Board XO Active-Only source >> + - description: Sleep clock source > > What happened to clock-names? > >> + > > I would assume these are required for the clock controller... and they > were before, so what happened? I dropped them in v2, as with switching the .c driver to use the index matching, they are no longer used. Konrad > > > Best regards, > Krzysztof
On 23/07/2022 22:56, Konrad Dybcio wrote: > > > On 23.07.2022 19:46, Krzysztof Kozlowski wrote: >> On 23/07/2022 12:01, Konrad Dybcio wrote: >>> Add device tree bindings for global clock controller for SM6375 SoCs. >>> >>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> >>> --- >>> Changes since v2: >>> - reference qcom,gcc.yaml >>> >>> .../bindings/clock/qcom,sm6375-gcc.yaml | 48 ++++ >>> include/dt-bindings/clock/qcom,sm6375-gcc.h | 234 ++++++++++++++++++ >>> 2 files changed, 282 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml >>> create mode 100644 include/dt-bindings/clock/qcom,sm6375-gcc.h >>> >>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml >>> new file mode 100644 >>> index 000000000000..fb1c36888d18 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml >>> @@ -0,0 +1,48 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm Global Clock & Reset Controller Binding for SM6375 >>> + >>> +maintainers: >>> + - Konrad Dybcio <konrad.dybcio@somainline.org> >>> + >>> +description: | >>> + Qualcomm global clock control module which supports the clocks, resets and >>> + power domains on SM6375 >>> + >>> + See also: >>> + - dt-bindings/clock/qcom,sm6375-gcc.h >>> + >>> +allOf: >>> + - $ref: qcom,gcc.yaml# >>> + >>> +properties: >>> + compatible: >>> + const: qcom,sm6375-gcc >>> + >>> + clocks: >>> + items: >>> + - description: Board XO source >>> + - description: Board XO Active-Only source >>> + - description: Sleep clock source >> >> What happened to clock-names? >> >>> + >> >> I would assume these are required for the clock controller... and they >> were before, so what happened? > I dropped them in v2, as with switching the .c driver to use the > index matching, they are no longer used. OK, but what about clocks as required? Why aren't these now required? Best regards, Krzysztof
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index b42684703fbb..ea157723906a 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -27,6 +27,7 @@ # define PLL_VOTE_FSM_RESET BIT(21) # define PLL_UPDATE BIT(22) # define PLL_UPDATE_BYPASS BIT(23) +# define PLL_FSM_LEGACY_MODE BIT(24) # define PLL_OFFLINE_ACK BIT(28) # define ALPHA_PLL_ACK_LATCH BIT(29) # define PLL_ACTIVE_FLAG BIT(30) @@ -1102,6 +1103,10 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); } + if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) + regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, + PLL_FSM_LEGACY_MODE); + regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, PLL_UPDATE_BYPASS); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 447efb82fe59..b15a62cb8e36 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -70,9 +70,10 @@ struct clk_alpha_pll { const struct pll_vco *vco_table; size_t num_vco; -#define SUPPORTS_OFFLINE_REQ BIT(0) -#define SUPPORTS_FSM_MODE BIT(2) +#define SUPPORTS_OFFLINE_REQ BIT(0) +#define SUPPORTS_FSM_MODE BIT(2) #define SUPPORTS_DYNAMIC_UPDATE BIT(3) +#define SUPPORTS_FSM_LEGACY_MODE BIT(4) u8 flags; struct clk_regmap clkr;
This is used on at least SM6375 and its variations. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> --- No changes since v1/v2 drivers/clk/qcom/clk-alpha-pll.c | 5 +++++ drivers/clk/qcom/clk-alpha-pll.h | 5 +++-- 2 files changed, 8 insertions(+), 2 deletions(-)