diff mbox series

[RFC,4/9] clk: qcom: alpha-pll: Add macros to collapse definition

Message ID 20220726142303.4126434-5-abel.vesa@linaro.org
State New
Headers show
Series [RFC,1/9] clk: qcom: qcc-sdm845: Collapse gdsc structs into macros | expand

Commit Message

Abel Vesa July 26, 2022, 2:22 p.m. UTC 
Add macros for a visually more compact alpha-pll clocks definition,
one for alpha-pll and one for alpha-pll postdiv. These are only the ones
used by gcc-sdm845 driver. More will be added later on.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
 drivers/clk/qcom/clk-alpha-pll.h | 61 ++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 447efb82fe59..1bf7a3ecb7f1 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -127,6 +127,67 @@  struct alpha_pll_config {
 	u32 vco_mask;
 };
 
+#define __DEFINE_QCOM_CC_CLK_ALPHA_PLL(_name, _offset, _regs,			\
+					_enable_reg, _enable_mask,		\
+					_parent_fw_name, _flags, _ops)		\
+	static struct clk_alpha_pll _name = {					\
+		.offset = _offset,						\
+		.regs = _regs,							\
+		.clkr = {							\
+			.enable_reg = _enable_reg,				\
+			.enable_mask = _enable_mask,				\
+			.hw.init = &(struct clk_init_data){			\
+				.name = #_name,					\
+				.parent_data = &(const struct clk_parent_data){	\
+					.fw_name = _parent_fw_name,		\
+					.name = _parent_fw_name,		\
+				},						\
+				.num_parents = 1,				\
+				.ops = _ops,					\
+				.flags = _flags,				\
+			},							\
+		},								\
+	}
+
+#define __DEFINE_QCOM_CC_CLK_ALPHA_PLL_POSTDIV(_name, _offset,			\
+					_post_div_shift, _post_div_table,	\
+					_width, _regs,				\
+					_parent_hws, _flags, _ops)		\
+	static struct clk_alpha_pll_postdiv _name = {				\
+		.offset = _offset,						\
+		.post_div_shift = _post_div_shift,				\
+		.post_div_table = _post_div_table,				\
+		.num_post_div = ARRAY_SIZE(_post_div_table),			\
+		.width = _width,						\
+		.regs = _regs,							\
+		.clkr.hw.init = &(struct clk_init_data){			\
+			.name = #_name,						\
+			.parent_hws = (const struct clk_hw*[]){			\
+				_parent_hws,					\
+			},							\
+			.num_parents = 1,					\
+			.ops = _ops,						\
+			.flags = _flags,					\
+		},								\
+	}
+
+#define DEFINE_QCOM_CC_CLK_ALPHA_PLL(_name, _offset,				\
+					_enable_reg, _enable_mask,		\
+					_parent_fw_name)			\
+	__DEFINE_QCOM_CC_CLK_ALPHA_PLL(_name, _offset,				\
+				clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],	\
+				_enable_reg, _enable_mask,			\
+				_parent_fw_name, 0,				\
+				&clk_alpha_pll_fixed_fabia_ops)
+
+#define DEFINE_QCOM_CC_CLK_ALPHA_PLL_POSTDIV(_name, _offset,			\
+					_post_div_shift, _post_div_table,	\
+					_width, _parent_hws)			\
+	__DEFINE_QCOM_CC_CLK_ALPHA_PLL_POSTDIV(_name, _offset,			\
+				_post_div_shift, _post_div_table, _width,	\
+				clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],	\
+				_parent_hws, 0,	&clk_alpha_pll_postdiv_fabia_ops)
+
 extern const struct clk_ops clk_alpha_pll_ops;
 extern const struct clk_ops clk_alpha_pll_fixed_ops;
 extern const struct clk_ops clk_alpha_pll_hwfsm_ops;