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[v3,2/2] serial: pl011: Add reg-io-width parameters

Message ID 20220822130333.5353-3-shubhrajyoti.datta@amd.com
State New
Headers show
Series serial: pl011: Add xilinx uart | expand

Commit Message

Shubhrajyoti Datta Aug. 22, 2022, 1:03 p.m. UTC 
From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>

Some of the implementations can read only 32 bits because of
the interface limitations of the port they are connected to.
Add a parameter reg-io-width for supporting such platforms.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
v3:
use reg-io-width

 drivers/tty/serial/amba-pl011.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
diff mbox series

Patch

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 16a21422ddce..735451e44fbb 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -2775,6 +2775,7 @@  static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 	struct uart_amba_port *uap;
 	struct vendor_data *vendor = id->data;
 	int portnr, ret;
+	u32 val;
 
 	portnr = pl011_find_free_port();
 	if (portnr < 0)
@@ -2798,6 +2799,21 @@  static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 	uap->port.rs485_config = pl011_rs485_config;
 	snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
 
+	if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) {
+		switch (val) {
+		case 1:
+			uap->port.iotype = UPIO_MEM;
+			break;
+		case 4:
+			uap->port.iotype = UPIO_MEM32;
+			break;
+		default:
+			dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n",
+				 val);
+			return -EINVAL;
+		}
+	}
+
 	ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
 	if (ret)
 		return ret;