| Message ID | 20220830183448.18997-1-krzysztof.kozlowski@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [GIT,PULL] clk: samsung: for v6.1 | expand |
Quoting Krzysztof Kozlowski (2022-08-30 11:34:48) > Hi Stephen, > > Samsung clocks from a new tree. I hope we can meet on some Linux conference for > a key signing. :) I'll be at LPC next month. > > Best regards, > Krzysztof > > > The following changes since commit 568035b01cfb107af8d2e4bd2fb9aea22cf5b868: > > Linux 6.0-rc1 (2022-08-14 15:50:18 -0700) > > are available in the Git repository at: > > https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-clk-6.1 > > for you to fetch changes up to ef96c458888fa2a329b14efc7991530f645fbddb: > > clk: samsung: MAINTAINERS: add Krzysztof Kozlowski (2022-08-24 16:10:22 +0300) > > ---------------------------------------------------------------- Thanks. Pulled into clk-next
Hi Stephen, Samsung clocks from a new tree. I hope we can meet on some Linux conference for a key signing. :) Best regards, Krzysztof The following changes since commit 568035b01cfb107af8d2e4bd2fb9aea22cf5b868: Linux 6.0-rc1 (2022-08-14 15:50:18 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-clk-6.1 for you to fetch changes up to ef96c458888fa2a329b14efc7991530f645fbddb: clk: samsung: MAINTAINERS: add Krzysztof Kozlowski (2022-08-24 16:10:22 +0300) ---------------------------------------------------------------- Samsung SoC clock drivers changes for 6.1 1. Exynos7885: add FSYS, TREX and MFC clock controllers. 2. Exynos850: add IS and AUD (audio) clock controllers with bindings. 3. ExynosAutov9: add FSYS clock controllers with bindings. 4. ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock controllers, due to duplicated entries. This is an acceptable ABI break: recently developed/added platform so without legacies, acked by known users/developers. 5. ExynosAutov9: add few missing Peric 0/1 gates. 6. ExynosAutov9: correct register offsets of few Peric 0/1 clocks. 7. Minor code improvements (use of_device_get_match_data() helper, code style). 8. Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he already maintainers that architecture/platform. ---------------------------------------------------------------- Chanho Park (8): dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 dt-bindings: clock: exynosautov9: add fys0 clock definitions dt-bindings: clock: exynosautov9: add fsys1 clock definitions dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1 clk: samsung: exynosautov9: add missing gate clks for peric0/c1 clk: samsung: exynosautov9: correct register offsets of peric0/c1 clk: samsung: exynosautov9: add fsys0 clock support clk: samsung: exynosautov9: add fsys1 clock support David Virag (2): clk: samsung: exynos7885: Implement CMU_FSYS domain clk: samsung: exynos7885: Add TREX clocks Krzysztof Kozlowski (2): Merge branch 'for-v6.0/samsung-clk-dt-bindings' into next/clk clk: samsung: MAINTAINERS: add Krzysztof Kozlowski Minghao Chi (CGEL ZTE) (1): clk: samsung: exynos-clkout: Use of_device_get_match_data() Sam Protsenko (7): dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD dt-bindings: clock: exynos850: Add Exynos850 CMU_IS dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL clk: samsung: exynos850: Style fixes clk: samsung: exynos850: Implement CMU_AUD domain clk: samsung: exynos850: Implement CMU_IS domain clk: samsung: exynos850: Implement CMU_MFCMSCL domain .../bindings/clock/samsung,exynos850-clock.yaml | 69 +++ .../bindings/clock/samsung,exynosautov9-clock.yaml | 44 ++ MAINTAINERS | 2 + drivers/clk/samsung/clk-exynos-clkout.c | 6 +- drivers/clk/samsung/clk-exynos7885.c | 207 ++++++- drivers/clk/samsung/clk-exynos850.c | 682 ++++++++++++++++++++- drivers/clk/samsung/clk-exynosautov9.c | 401 +++++++++++- include/dt-bindings/clock/exynos850.h | 136 +++- include/dt-bindings/clock/samsung,exynosautov9.h | 128 +++- 9 files changed, 1620 insertions(+), 55 deletions(-)