@@ -178,7 +178,7 @@
#define ECC_CEADDR0_RNK_MASK BIT(24)
#define ECC_CEADDR1_BNKGRP_MASK 0x3000000
#define ECC_CEADDR1_BNKNR_MASK 0x70000
-#define ECC_CEADDR1_BLKNR_MASK 0xFFF
+#define ECC_CEADDR1_COL_MASK 0xFFF
#define ECC_CEADDR1_BNKGRP_SHIFT 24
#define ECC_CEADDR1_BNKNR_SHIFT 16
@@ -276,7 +276,6 @@
* @bitpos: Bit position.
* @data: Data causing the error.
* @bankgrpnr: Bank group number.
- * @blknr: Block number.
*/
struct ecc_error_info {
u32 row;
@@ -285,7 +284,6 @@ struct ecc_error_info {
u32 bitpos;
u32 data;
u32 bankgrpnr;
- u32 blknr;
};
/**
@@ -438,7 +436,7 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv)
ECC_CEADDR1_BNKNR_SHIFT;
p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
ECC_CEADDR1_BNKGRP_SHIFT;
- p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
+ p->ceinfo.col = (regval & ECC_CEADDR1_COL_MASK);
p->ceinfo.data = readl(base + ECC_CSYND0_OFST);
edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n",
readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST),
@@ -454,7 +452,7 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv)
ECC_CEADDR1_BNKGRP_SHIFT;
p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
ECC_CEADDR1_BNKNR_SHIFT;
- p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
+ p->ueinfo.col = (regval & ECC_CEADDR1_COL_MASK);
p->ueinfo.data = readl(base + ECC_UESYND0_OFST);
out:
@@ -486,10 +484,9 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
pinf = &p->ceinfo;
if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
- "DDR ECC error type:%s Row %d Bank %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0x%08x",
- "CE", pinf->row, pinf->bank,
- pinf->bankgrpnr, pinf->blknr,
- pinf->bitpos, pinf->data);
+ "DDR ECC error type:%s Row %d Col %d Bank %d BankGroup Number %d Bit Position: %d Data: 0x%08x",
+ "CE", pinf->row, pinf->col, pinf->bank,
+ pinf->bankgrpnr, pinf->bitpos, pinf->data);
} else {
snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
"DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x",
@@ -506,9 +503,9 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
pinf = &p->ueinfo;
if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
- "DDR ECC error type :%s Row %d Bank %d BankGroup Number %d Block Number %d",
- "UE", pinf->row, pinf->bank,
- pinf->bankgrpnr, pinf->blknr);
+ "DDR ECC error type :%s Row %d Col %d Bank %d BankGroup Number %d",
+ "UE", pinf->row, pinf->col, pinf->bank,
+ pinf->bankgrpnr);
} else {
snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
"DDR ECC error type :%s Row %d Bank %d Col %d ",
Even though the ECC(C|U)ADDR1 CSR description indeed says it's a "Block number" in the DW uMCTL2 DDRC hw reference manuals, the corresponding register field name (ECC(C|U)ADDR1.ecc_(un)corr_col) and the rest of the hw documentation refer to the field as the SDRAM address column. Thus let's use the already available ecc_error_info.col field to read the column number to and drop the questionable ecc_error_info.blknr field for good. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- drivers/edac/synopsys_edac.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-)