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[PATCHv2,1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon"

Message ID 20220922220308.609422-2-dinguyen@kernel.org
State New
Headers show
Series mmc: socfpga: add method to configure clk-phase | expand

Commit Message

Dinh Nguyen Sept. 22, 2022, 10:03 p.m. UTC 
Document the optional "altr,sysmgr-syscon" binding that is used to
access the System Manager register that controls the SDMMC clock
phase.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: added
---
 .../devicetree/bindings/mmc/synopsys-dw-mshc.yaml    | 12 ++++++++++++
 1 file changed, 12 insertions(+)
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Patch

diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
index ae6d6fca79e2..aece6a337262 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
@@ -38,6 +38,18 @@  properties:
       - const: biu
       - const: ciu
 
+  altr,sysmgr-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to the sysmgr node
+          - description: register offset that controls the SDMMC clock phase
+    description:
+      Contains the phandle to System Manager block that contains
+      the SDMMC clock-phase control register. The first value is the pointer
+      to the sysmgr and the 2nd value is the register offset for the SDMMC
+      clock phase register.
+
 required:
   - compatible
   - reg