@@ -25,6 +25,9 @@
#include <linux/mmc/slot-gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/ktime.h>
+#ifdef CONFIG_IOMMU_API
+#include <linux/iommu.h>
+#endif
#include <soc/tegra/common.h>
@@ -94,6 +97,8 @@
#define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec
#define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31)
+#define SDHCI_TEGRA_CIF2AXI_CTRL_0 0x1fc
+
#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
@@ -121,6 +126,7 @@
#define NVQUIRK_HAS_TMCLK BIT(10)
#define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11)
+#define NVQUIRK_PROGRAM_STREAMID BIT(12)
/* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
#define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000
@@ -128,6 +134,8 @@
#define SDHCI_TEGRA_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
SDHCI_TRNS_BLK_CNT_EN | \
SDHCI_TRNS_DMA)
+#define SDHCI_TEGRA_STREAMID_MASK 0xff
+#define SDHCI_TEGRA_WRITE_STREAMID_SHIFT 0x8
struct sdhci_tegra_soc_data {
const struct sdhci_pltfm_data *pdata;
@@ -177,6 +185,9 @@ struct sdhci_tegra {
bool enable_hwcq;
unsigned long curr_clk_rate;
u8 tuned_tap_delay;
+#ifdef CONFIG_IOMMU_API
+ u32 streamid;
+#endif
};
static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
@@ -1564,6 +1575,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra234 = {
NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
NVQUIRK_ENABLE_SDR50 |
NVQUIRK_ENABLE_SDR104 |
+ NVQUIRK_PROGRAM_STREAMID |
NVQUIRK_HAS_TMCLK,
.min_tap_delay = 95,
.max_tap_delay = 111,
@@ -1636,6 +1648,9 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
struct sdhci_host *host;
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_tegra *tegra_host;
+#ifdef CONFIG_IOMMU_API
+ struct iommu_fwspec *fwspec;
+#endif
struct clk *clk;
int rc;
@@ -1775,6 +1790,25 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
if (rc)
goto err_add_host;
+ /* Program MC streamID for DMA transfers */
+#ifdef CONFIG_IOMMU_API
+ if (soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) {
+ fwspec = dev_iommu_fwspec_get(&pdev->dev);
+ if (fwspec == NULL) {
+ dev_warn(mmc_dev(host->mmc),
+ "iommu fwspec is NULL, continue without stream ID\n");
+ } else {
+ tegra_host->streamid = fwspec->ids[0] & 0xffff;
+ tegra_sdhci_writel(host, (tegra_host->streamid &
+ SDHCI_TEGRA_STREAMID_MASK) |
+ ((tegra_host->streamid <<
+ SDHCI_TEGRA_WRITE_STREAMID_SHIFT)
+ & SDHCI_TEGRA_STREAMID_MASK),
+ SDHCI_TEGRA_CIF2AXI_CTRL_0);
+ }
+ }
+#endif
+
return 0;
err_add_host:
@@ -1861,6 +1895,10 @@ static int sdhci_tegra_suspend(struct device *dev)
static int sdhci_tegra_resume(struct device *dev)
{
struct sdhci_host *host = dev_get_drvdata(dev);
+#ifdef CONFIG_IOMMU_API
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
+#endif
int ret;
ret = mmc_gpio_set_cd_wake(host->mmc, false);
@@ -1871,6 +1909,15 @@ static int sdhci_tegra_resume(struct device *dev)
if (ret)
return ret;
+ /* Re-program MC streamID for DMA transfers */
+#ifdef CONFIG_IOMMU_API
+ if (tegra_host->soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) {
+ tegra_sdhci_writel(host, tegra_host->streamid |
+ (tegra_host->streamid << 8),
+ SDHCI_TEGRA_CIF2AXI_CTRL_0);
+ }
+#endif
+
ret = sdhci_resume_host(host);
if (ret)
goto disable_clk;