| Message ID | 20221011080359.76220-1-p.rajanbabu@samsung.com |
|---|---|
| State | New |
| Headers | show |
| Series | [V2] arm64: dts: fix drive strength macros as per FSD HW UM | expand |
On 11/10/2022 04:03, Padmanabhan Rajanbabu wrote: > Drive strength macros defined for FSD platform is not reflecting actual > name and values as per HW UM. FSD SoC pinctrl has following four levels of s/name/names/ > drive-strength and their corresponding values: > Level-1 <-> 0 > Level-2 <-> 1 > Level-4 <-> 2 > Level-6 <-> 3 > > The commit 684dac402f21 ("arm64: dts: fsd: Add initial pinctrl support") > used drive strength macros defined for Exynos4 SoC family. For some IPs > the macros values of Exynos4 matched and worked well, but Exynos4 SoC > family drive-strength (names and values) is not exactly matching with > FSD SoC. > > Fix the drive strength macros to reflect actual names and values given > in FSD HW UM. This also ensures that the existing peripherals in device > tree file is using correct drive strength MACROs to function as > expected. > > Fixes: 684dac402f21 ("arm64: dts: fsd: Add initial pinctrl support") > Signed-off-by: Padmanabhan Rajanbabu <p.rajanbabu@samsung.com> > --- Rest of commit msg looks ok. > arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 34 +++++++++++----------- > arch/arm64/boot/dts/tesla/fsd-pinctrl.h | 6 ++-- > 2 files changed, 20 insertions(+), 20 deletions(-) > > diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi > index d0abb9aa0e9e..e3852c946352 100644 > --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi > +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi > @@ -55,14 +55,14 @@ > samsung,pins = "gpf5-0"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_NONE>; > - samsung,pin-drv = <FSD_PIN_DRV_LV2>; > + samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > ufs_refclk_out: ufs-refclk-out-pins { > samsung,pins = "gpf5-1"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_NONE>; > - samsung,pin-drv = <FSD_PIN_DRV_LV2>; > + samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > }; > > @@ -239,105 +239,105 @@ > samsung,pins = "gpb6-1"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; > - samsung,pin-drv = <FSD_PIN_DRV_LV2>; > + samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > pwm1_out: pwm1-out-pins { > samsung,pins = "gpb6-5"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; > - samsung,pin-drv = <FSD_PIN_DRV_LV2>; > + samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > hs_i2c0_bus: hs-i2c0-bus-pins { > samsung,pins = "gpb0-0", "gpb0-1"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; > - samsung,pin-drv = <FSD_PIN_DRV_LV1>; > + samsung,pin-drv = <FSD_PIN_DRV_LV4>; You are now changing both the value for register and the meaning (name). Your commit msg indicated that the names are not correct, not the values. Based on the commit msg, I expect the DTBs are the same. Are they? If not, it these are two different commits with their own explanations/reasoning. Best regards, Krzysztof
>-----Original Message----- >From: Padmanabhan Rajanbabu [mailto:p.rajanbabu@samsung.com] >Sent: Tuesday, October 11, 2022 1:34 PM >To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; >alim.akhtar@samsung.com; chanho61.park@samsung.com; >linus.walleij@linaro.org; pankaj.dubey@samsung.com >Cc: devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux- >samsung-soc@vger.kernel.org; Padmanabhan Rajanbabu ><p.rajanbabu@samsung.com> >Subject: [PATCH V2] arm64: dts: fix drive strength macros as per FSD HW UM > >Drive strength macros defined for FSD platform is not reflecting actual name >and values as per HW UM. FSD SoC pinctrl has following four levels of drive- >strength and their corresponding values: >Level-1 <-> 0 >Level-2 <-> 1 >Level-4 <-> 2 >Level-6 <-> 3 > >The commit 684dac402f21 ("arm64: dts: fsd: Add initial pinctrl support") used >drive strength macros defined for Exynos4 SoC family. For some IPs the >macros values of Exynos4 matched and worked well, but Exynos4 SoC family >drive-strength (names and values) is not exactly matching with FSD SoC. > >Fix the drive strength macros to reflect actual names and values given in FSD >HW UM. This also ensures that the existing peripherals in device tree file is >using correct drive strength MACROs to function as expected. > >Fixes: 684dac402f21 ("arm64: dts: fsd: Add initial pinctrl support") >Signed-off-by: Padmanabhan Rajanbabu <p.rajanbabu@samsung.com> >--- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> > arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 34 +++++++++++----------- > arch/arm64/boot/dts/tesla/fsd-pinctrl.h | 6 ++-- > 2 files changed, 20 insertions(+), 20 deletions(-) > >diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi >b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi >index d0abb9aa0e9e..e3852c946352 100644 >--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi >+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi >@@ -55,14 +55,14 @@ > samsung,pins = "gpf5-0"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_NONE>; >- samsung,pin-drv = <FSD_PIN_DRV_LV2>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > ufs_refclk_out: ufs-refclk-out-pins { > samsung,pins = "gpf5-1"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_NONE>; >- samsung,pin-drv = <FSD_PIN_DRV_LV2>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > }; > >@@ -239,105 +239,105 @@ > samsung,pins = "gpb6-1"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; >- samsung,pin-drv = <FSD_PIN_DRV_LV2>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > pwm1_out: pwm1-out-pins { > samsung,pins = "gpb6-5"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; >- samsung,pin-drv = <FSD_PIN_DRV_LV2>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > hs_i2c0_bus: hs-i2c0-bus-pins { > samsung,pins = "gpb0-0", "gpb0-1"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; >- samsung,pin-drv = <FSD_PIN_DRV_LV1>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > hs_i2c1_bus: hs-i2c1-bus-pins { > samsung,pins = "gpb0-2", "gpb0-3"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; >- samsung,pin-drv = <FSD_PIN_DRV_LV1>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > hs_i2c2_bus: hs-i2c2-bus-pins { > samsung,pins = "gpb0-4", "gpb0-5"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; >- samsung,pin-drv = <FSD_PIN_DRV_LV1>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > hs_i2c3_bus: hs-i2c3-bus-pins { > samsung,pins = "gpb0-6", "gpb0-7"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; >- samsung,pin-drv = <FSD_PIN_DRV_LV1>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > hs_i2c4_bus: hs-i2c4-bus-pins { > samsung,pins = "gpb1-0", "gpb1-1"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; >- samsung,pin-drv = <FSD_PIN_DRV_LV1>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > hs_i2c5_bus: hs-i2c5-bus-pins { > samsung,pins = "gpb1-2", "gpb1-3"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; >- samsung,pin-drv = <FSD_PIN_DRV_LV1>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > hs_i2c6_bus: hs-i2c6-bus-pins { > samsung,pins = "gpb1-4", "gpb1-5"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; >- samsung,pin-drv = <FSD_PIN_DRV_LV1>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > hs_i2c7_bus: hs-i2c7-bus-pins { > samsung,pins = "gpb1-6", "gpb1-7"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; >- samsung,pin-drv = <FSD_PIN_DRV_LV1>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > uart0_data: uart0-data-pins { > samsung,pins = "gpb7-0", "gpb7-1"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_NONE>; >- samsung,pin-drv = <FSD_PIN_DRV_LV1>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > uart1_data: uart1-data-pins { > samsung,pins = "gpb7-4", "gpb7-5"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_NONE>; >- samsung,pin-drv = <FSD_PIN_DRV_LV1>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > spi0_bus: spi0-bus-pins { > samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; >- samsung,pin-drv = <FSD_PIN_DRV_LV1>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > spi1_bus: spi1-bus-pins { > samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; >- samsung,pin-drv = <FSD_PIN_DRV_LV1>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > > spi2_bus: spi2-bus-pins { > samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3"; > samsung,pin-function = <FSD_PIN_FUNC_2>; > samsung,pin-pud = <FSD_PIN_PULL_UP>; >- samsung,pin-drv = <FSD_PIN_DRV_LV1>; >+ samsung,pin-drv = <FSD_PIN_DRV_LV4>; > }; > }; > >diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.h >b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h >index 6ffbda362493..c397d02208a0 100644 >--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.h >+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h >@@ -16,9 +16,9 @@ > #define FSD_PIN_PULL_UP 3 > > #define FSD_PIN_DRV_LV1 0 >-#define FSD_PIN_DRV_LV2 2 >-#define FSD_PIN_DRV_LV3 1 >-#define FSD_PIN_DRV_LV4 3 >+#define FSD_PIN_DRV_LV2 1 >+#define FSD_PIN_DRV_LV4 2 >+#define FSD_PIN_DRV_LV6 3 > > #define FSD_PIN_FUNC_INPUT 0 > #define FSD_PIN_FUNC_OUTPUT 1 >-- >2.17.1
> -----Original Message----- > From: Krzysztof Kozlowski [mailto:krzysztof.kozlowski@linaro.org] > Sent: 12 October 2022 02:28 AM > To: Padmanabhan Rajanbabu <p.rajanbabu@samsung.com>; > robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > alim.akhtar@samsung.com; chanho61.park@samsung.com; > linus.walleij@linaro.org; pankaj.dubey@samsung.com > Cc: devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux- > samsung-soc@vger.kernel.org > Subject: Re: [PATCH V2] arm64: dts: fix drive strength macros as per FSD HW > UM > > On 11/10/2022 04:03, Padmanabhan Rajanbabu wrote: > > Drive strength macros defined for FSD platform is not reflecting > > actual name and values as per HW UM. FSD SoC pinctrl has following > > four levels of > > s/name/names/ Okay. > > > drive-strength and their corresponding values: > > Level-1 <-> 0 > > Level-2 <-> 1 > > Level-4 <-> 2 > > Level-6 <-> 3 > > > > The commit 684dac402f21 ("arm64: dts: fsd: Add initial pinctrl > > support") used drive strength macros defined for Exynos4 SoC family. > > For some IPs the macros values of Exynos4 matched and worked well, but > > Exynos4 SoC family drive-strength (names and values) is not exactly > > matching with FSD SoC. > > > > Fix the drive strength macros to reflect actual names and values given > > in FSD HW UM. This also ensures that the existing peripherals in > > device tree file is using correct drive strength MACROs to function as > > expected. > > > > Fixes: 684dac402f21 ("arm64: dts: fsd: Add initial pinctrl support") > > Signed-off-by: Padmanabhan Rajanbabu <p.rajanbabu@samsung.com> > > --- > > Rest of commit msg looks ok. > > > arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 34 +++++++++++----------- > > arch/arm64/boot/dts/tesla/fsd-pinctrl.h | 6 ++-- > > 2 files changed, 20 insertions(+), 20 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi > > b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi > > index d0abb9aa0e9e..e3852c946352 100644 > > --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi > > +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi > > @@ -55,14 +55,14 @@ > > samsung,pins = "gpf5-0"; > > samsung,pin-function = <FSD_PIN_FUNC_2>; > > samsung,pin-pud = <FSD_PIN_PULL_NONE>; > > - samsung,pin-drv = <FSD_PIN_DRV_LV2>; > > + samsung,pin-drv = <FSD_PIN_DRV_LV4>; > > }; > > > > ufs_refclk_out: ufs-refclk-out-pins { > > samsung,pins = "gpf5-1"; > > samsung,pin-function = <FSD_PIN_FUNC_2>; > > samsung,pin-pud = <FSD_PIN_PULL_NONE>; > > - samsung,pin-drv = <FSD_PIN_DRV_LV2>; > > + samsung,pin-drv = <FSD_PIN_DRV_LV4>; > > }; > > }; > > > > @@ -239,105 +239,105 @@ > > samsung,pins = "gpb6-1"; > > samsung,pin-function = <FSD_PIN_FUNC_2>; > > samsung,pin-pud = <FSD_PIN_PULL_UP>; > > - samsung,pin-drv = <FSD_PIN_DRV_LV2>; > > + samsung,pin-drv = <FSD_PIN_DRV_LV4>; > > }; > > > > pwm1_out: pwm1-out-pins { > > samsung,pins = "gpb6-5"; > > samsung,pin-function = <FSD_PIN_FUNC_2>; > > samsung,pin-pud = <FSD_PIN_PULL_UP>; > > - samsung,pin-drv = <FSD_PIN_DRV_LV2>; > > + samsung,pin-drv = <FSD_PIN_DRV_LV4>; > > }; > > > > hs_i2c0_bus: hs-i2c0-bus-pins { > > samsung,pins = "gpb0-0", "gpb0-1"; > > samsung,pin-function = <FSD_PIN_FUNC_2>; > > samsung,pin-pud = <FSD_PIN_PULL_UP>; > > - samsung,pin-drv = <FSD_PIN_DRV_LV1>; > > + samsung,pin-drv = <FSD_PIN_DRV_LV4>; > > You are now changing both the value for register and the meaning (name). > Your commit msg indicated that the names are not correct, not the values. > Based on the commit msg, I expect the DTBs are the same. Are they? If not, > it these are two different commits with their own explanations/reasoning. In some cases, yes, both name and values requires modification. I understood that I have to split this into two patches, correcting the MACRO names and values in one patch and fixing the drive strength for some of the IPs in other patch. > > Best regards, > Krzysztof
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi index d0abb9aa0e9e..e3852c946352 100644 --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -55,14 +55,14 @@ samsung,pins = "gpf5-0"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_NONE>; - samsung,pin-drv = <FSD_PIN_DRV_LV2>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; ufs_refclk_out: ufs-refclk-out-pins { samsung,pins = "gpf5-1"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_NONE>; - samsung,pin-drv = <FSD_PIN_DRV_LV2>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; }; @@ -239,105 +239,105 @@ samsung,pins = "gpb6-1"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV2>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; pwm1_out: pwm1-out-pins { samsung,pins = "gpb6-5"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV2>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c0_bus: hs-i2c0-bus-pins { samsung,pins = "gpb0-0", "gpb0-1"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c1_bus: hs-i2c1-bus-pins { samsung,pins = "gpb0-2", "gpb0-3"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c2_bus: hs-i2c2-bus-pins { samsung,pins = "gpb0-4", "gpb0-5"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c3_bus: hs-i2c3-bus-pins { samsung,pins = "gpb0-6", "gpb0-7"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c4_bus: hs-i2c4-bus-pins { samsung,pins = "gpb1-0", "gpb1-1"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c5_bus: hs-i2c5-bus-pins { samsung,pins = "gpb1-2", "gpb1-3"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c6_bus: hs-i2c6-bus-pins { samsung,pins = "gpb1-4", "gpb1-5"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c7_bus: hs-i2c7-bus-pins { samsung,pins = "gpb1-6", "gpb1-7"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; uart0_data: uart0-data-pins { samsung,pins = "gpb7-0", "gpb7-1"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_NONE>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; uart1_data: uart1-data-pins { samsung,pins = "gpb7-4", "gpb7-5"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_NONE>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; spi0_bus: spi0-bus-pins { samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; spi1_bus: spi1-bus-pins { samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; spi2_bus: spi2-bus-pins { samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; }; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.h b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h index 6ffbda362493..c397d02208a0 100644 --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.h +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h @@ -16,9 +16,9 @@ #define FSD_PIN_PULL_UP 3 #define FSD_PIN_DRV_LV1 0 -#define FSD_PIN_DRV_LV2 2 -#define FSD_PIN_DRV_LV3 1 -#define FSD_PIN_DRV_LV4 3 +#define FSD_PIN_DRV_LV2 1 +#define FSD_PIN_DRV_LV4 2 +#define FSD_PIN_DRV_LV6 3 #define FSD_PIN_FUNC_INPUT 0 #define FSD_PIN_FUNC_OUTPUT 1
Drive strength macros defined for FSD platform is not reflecting actual name and values as per HW UM. FSD SoC pinctrl has following four levels of drive-strength and their corresponding values: Level-1 <-> 0 Level-2 <-> 1 Level-4 <-> 2 Level-6 <-> 3 The commit 684dac402f21 ("arm64: dts: fsd: Add initial pinctrl support") used drive strength macros defined for Exynos4 SoC family. For some IPs the macros values of Exynos4 matched and worked well, but Exynos4 SoC family drive-strength (names and values) is not exactly matching with FSD SoC. Fix the drive strength macros to reflect actual names and values given in FSD HW UM. This also ensures that the existing peripherals in device tree file is using correct drive strength MACROs to function as expected. Fixes: 684dac402f21 ("arm64: dts: fsd: Add initial pinctrl support") Signed-off-by: Padmanabhan Rajanbabu <p.rajanbabu@samsung.com> --- arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 34 +++++++++++----------- arch/arm64/boot/dts/tesla/fsd-pinctrl.h | 6 ++-- 2 files changed, 20 insertions(+), 20 deletions(-)